| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-07-04 | update crate to rust 2018 | iximeow | |
| 2021-07-04 | support avx512 registers >=16 | iximeow | |
| 2021-07-04 | handle vzeroupper/vzeroall, reject vzero* with nonzero vvvv | iximeow | |
| 2021-07-04 | support xacquire/xrelease prefixing | iximeow | |
| 2021-07-04 | 16-bit addressing in protected mode may see avx512 masks too | iximeow | |
| 2021-07-04 | fix several incorrect tests and docs in 64- and 32-bit modes | iximeow | |
| 2021-07-03 | update protected_mode to match long_mode docs, apis | iximeow | |
| 2021-07-03 | update DecodeError impls | iximeow | |
| 2021-07-03 | document public members in long_mode | iximeow | |
| 2021-07-03 | write some dang docs, export `MemoryAccessSize` where you'll look for it | iximeow | |
| 2021-07-03 | more carefully test mmx operand sizes | iximeow | |
| 2021-07-03 | factor out MemoryAccessSize | iximeow | |
| 2021-07-03 | add tests for MemoryAccessSize, consistentify style on docs | iximeow | |
| 2021-07-03 | be more strict about denying invalid operands | iximeow | |
| 2021-07-03 | do not reject prefixed sgdt, add a TODO for xop | iximeow | |
| not that xop will ever be wanted, rip | |||
| 2021-07-03 | support AMD `sev_snp` | iximeow | |
| 2021-07-03 | clean up x86_32 and make interfaces match x86_64 | iximeow | |
| 2021-07-03 | prefixes on 0f01-series opcodes are more strict | iximeow | |
| 2021-07-03 | add hreset | iximeow | |
| 2021-07-03 | port over x86_64 improvements to x86_32 | iximeow | |
| 2021-07-03 | support pconfig/tme | iximeow | |
| 2021-07-02 | intel keylocker instructions that access memory have memory access sizes | iximeow | |
| 2021-07-02 | fix several strict rejection for several | iximeow | |
| 2021-07-02 | `Nothing` operand code must be decoded with operand_count=0 | iximeow | |
| 2021-07-01 | reallocate OperandCode, convert disparate registers to array | iximeow | |
| also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode. | |||
| 2021-07-01 | update yaxpeax-x86 to yaxpeax-arch 0.1.0 interfaces | iximeow | |
| 2021-06-29 | fix several lingering mem_size discrepancies | iximeow | |
| 2021-06-28 | remove old movsx/movzx-related memory size hacks | iximeow | |
| 2021-06-28 | clean up protected mode vex-related warnings | iximeow | |
| 2021-06-28 | remove a few operand cases | iximeow | |
| vex decoding is really intended to avoid explosions in code size more than anything... | |||
| 2021-06-28 | round out x86_32 support - avx2, avx, memory sizes | iximeow | |
| 2021-06-28 | protected mode memory sizes | iximeow | |
| also some long-mode cleanup in corresponding areas | |||
| 2021-06-27 | protected-mode avx512 | iximeow | |
| 2021-06-26 | awkward | iximeow | |
| i really didnt know rust could do this | |||
| 2021-05-07 | remove dead OperandSpec variants | iximeow | |
| 2021-05-07 | update yaxpeax-arch to 0.0.5, fix interface breakages | iximeow | |
| 2021-03-22 | and clean up some warnings | iximeow | |
| 2021-03-22 | port long-mode decoder updates to protected-mode | iximeow | |
| 2021-03-21 | make Opcode, Operand, and DecodeError non_exhaustive | iximeow | |
| in the future these can and will change (new operands, new instructions) and i would prefer they not be major breaking changes. applications can ignore them and probably do undesired variants anyway. if you want to write a 1120-variant match, are you me? why would you do this | |||
| 2021-01-15 | support xchg AX/reg0.1.5 | iximeow | |
| 2021-01-15 | fix several missing or invalid decodings among 0f01 opcodes | iximeow | |
| * `mwaitx`, `monitorx`, `rdpru`, and `clzero` are now supported * swapgs is no longer decoded in protected mode * rdpkru and wrpkru are no longer decoded if mod bits != 11 | |||
| 2020-10-27 | fix misdecode of instructions in opcode 0x800.1.3 | iximeow | |
| 2020-08-15 | add RegSpec constructors, consts, and const fns0.1.2 | iximeow | |
| 2020-08-15 | add register class constants to allow reasoning about register operands0.1.1 | iximeow | |
| also bump to 0.1.1 | |||
| 2020-08-09 | inaugural 0.1.0 release!0.1.0 | iximeow | |
| add doc comments for public items, record changelog, and lets ship this!! | |||
| 2020-08-09 | adjust public interface: public items should all be stable | iximeow | |
| `OperandCode` (obviously) wildly varies depending on how i feel on a given week, so it's now hidden to avoid people depending on numerical values of its discriminants. `RegisterBank` got a similar treatment with a new `RegisterClass` struct that's suitable for public use. | |||
| 2020-08-09 | reject instructions made invalid by lock prefixes | iximeow | |
| 2020-08-09 | support salc, get segment register numbers right | iximeow | |
| 2020-08-09 | add 32-bit-only instructions | iximeow | |
| 2020-08-09 | port updates to protected-mode decoder | iximeow | |
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index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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