| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 14 hours | actually support avx/f16c in per-uarch decoding | iximeow | |
| 14 hours | vmaskmovdqu, vmovq were also incorrect in some ways... | iximeow | |
| 14 hours | more general avx improvements | iximeow | |
| 14 hours | cleanup pass on vex-encoded instructions is going to be exciting | iximeow | |
| 14 hours | report memory access size for "monitor" | iximeow | |
| 14 hours | maskmov{q,dqu} memory access size | iximeow | |
| 14 hours | more precise about 0f0d prefetch/nop | iximeow | |
| 14 hours | fix table management instructions' ({l,s}{g,i,l}dt) mem_size | iximeow | |
| these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know! | |||
| 14 hours | more accurate mov seg-to-gpr operand size | iximeow | |
| 14 hours | push/pop for segment registers has implicit memory access | iximeow | |
| 14 hours | pushf, popf, enter, leave, xlat all have implicit memory access | iximeow | |
| also add "is_masked" to operand spec | |||
| 14 hours | add initial stats for disasm stats in all modes | iximeow | |
| 2026-02-14 | fair enough on those warnings | iximeow | |
| 2026-02-14 | type aliases make some of these signatures less egregious.. | iximeow | |
| 2025-06-01 | 3dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵ | iximeow | |
| tweaks too | |||
| 2025-06-01 | describe the per-isa extensions a bit better | iximeow | |
| 2025-06-01 | revise_instruction is the same on all bitnesses, so macro it too | iximeow | |
| 2025-06-01 | DecodeEverything wasn't useful, no better than InstDecoder::default()?? | iximeow | |
| 2025-06-01 | cpu feature bits are the same across 64/32/16-bit | iximeow | |
| 2025-06-01 | expand isa feature selection to more bits | iximeow | |
| this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory | |||
| 2024-06-24 | document one more stray unsafe | iximeow | |
| 2024-06-24 | justify the current max instruction length | iximeow | |
| this is also checked by a new fuzz target | |||
| 2024-06-24 | consistently enter register/number/opcode spans | iximeow | |
| 2024-06-24 | rename most operand variants, make them structy rather than tupley | iximeow | |
| 2024-06-23 | remove selects_cs(), cs() now does the right thing | iximeow | |
| 2024-06-23 | fix several sources of dead code warnings in various crate configs | iximeow | |
| 2024-06-23 | remove yaxpeax-x86 safer_unchecked.rs, it is now in yaxpeax-arch | iximeow | |
| 2024-06-23 | cfg_attr wants feature, not features plural | iximeow | |
| 2024-06-23 | last vestiges of initial perf experiments | iximeow | |
| 2024-06-23 | another fuzz bug | iximeow | |
| 2024-06-23 | fuzz caught negation bug | iximeow | |
| 2024-06-23 | InstructionTextBuffer for all three modes, adjust fuzzer to match | iximeow | |
| 2024-06-23 | add additional `call` test cases | iximeow | |
| fix 32-bit 66-prefixed ff /2 call not having 16-bit operands fix momentary regression in rendering `call` instructions to string | |||
| 2024-06-23 | forward long deprecation allowances as appropriate | iximeow | |
| 2024-06-23 | normalize imports, pull safer_unchecked from yaxpeax-arch | iximeow | |
| 2024-06-23 | fix inlining attributes re. profiling flag in protected_mode | iximeow | |
| 2024-06-23 | adapt the rest of formating changes to protected_mode | iximeow | |
| 2024-06-23 | fix AbsoluteFarAddress being tagged as a memory operand | iximeow | |
| 2024-06-23 | adapt OperandVisitor to protected mode too | iximeow | |
| 2024-06-23 | actually use new can_lock in 32b and 16b modes | iximeow | |
| 2024-06-23 | actually use new can_rep in 32b and 16b modes | iximeow | |
| 2024-06-23 | port opcode helpers and reordering to 32-bit and 16-bit decoders | iximeow | |
| 2024-06-23 | add more conditional inlining for 32-bit and 16-bit decoders | iximeow | |
| 2024-04-02 | display opt: mem size labels and minor segment reporting changes | iximeow | |
| for mem size labels: add one new "BUG" entry at the start of the array so `mem_size` does not need to be adjusted before being used to look up a string from the `MEM_SIZE_STRINGS` array. it's hard to measure the direct benefit of this, but it shrinks codegen size by a bit and simplfies a bit of assembly.... for segment reporting changes: stos/scas/lods do not actually need special segment override logic. instead, set their use of `es` when decoded, if appropriate. this is potentially ambiguous; in non-64bit modes the sequence `26aa` would decode as `stos` with explicit `es` prefix. this is now identical to simply decoding `aa`, which now also reports that there is an explicit `es` prefix even though there is no prefix on tne instruction. on the other hand, the prefix-reported segment now more accurately describes the memory selector through which memory accesses will happen. seems ok? | |||
| 2023-12-16 | fix hreset being disassembled as having second operand of "Nothing" | iximeow | |
| just report it having one operand... | |||
| 2023-07-24 | fix handling of lar/lsl source register | iximeow | |
| 2023-07-23 | fix inconsistently-poreted memory access size of vcvt{,t}{sd,si} | iximeow | |
| 2023-07-23 | fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit) | iximeow | |
| 2023-07-16 | fix indentation | iximeow | |
| 2023-07-16 | unify 64-/32-bit more | iximeow | |
 |
index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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