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path: root/src/real_mode/mod.rs
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13 hourssome doc comments covered incorrect modesHEADno-gods-no-iximeow
15 hoursadd DisplayRules, docs, doc tests, ..iximeow
this includes `trait DisplayRules` as a generic mechanism to control parts of instruction printing, a `DefaultRules` for the existing formatting style, and `AbsoluteAddressFormatter` to print instructions as at some location in an address space.
15 hoursfix some forms of lss/lfs/lgs having incorrectly-small memory sizesiximeow
15 hoursprotected/real mode lfs/lgs/lssiximeow
15 hourspextr*/pinsr*/insertps/extrps immediate is now u8 instead of i8iximeow
15 hoursfix seam, user-ipi, {rd,wr}{fs,gs}base instructions decoding outside 64b modeiximeow
15 hoursadd MASM-style formatting support in all modesiximeow
this includes a mildly nightmarish bit of test harness to compare against ml.exe/ml64.exe/dumpbin.exe, which in turn chased out a bunch of bugs. yay!
14 daysthe weird 64b movq thing was a capstone bug all along?!iximeow
14 daysfix several instructions' incorrect memory or op2 sizeiximeow
14 daysrename rne-sae to rn-saeiximeow
14 daysMake invalid instruction constructors actually return invalid instructionsSamuel Arnold
As opposed to nops.
2026-05-26fix jrcxz/jecxz/jcxz having "two operands"iximeow
2026-05-25push/pop width in 16/32-bit modes are receptive to operand width prefixiximeow
2026-05-25reject arpl in 16-bit decodingiximeow
2026-05-25and some prefix helpers should be pubiximeow
2026-05-25j*cxz/pusha/popa alternate size formsiximeow
these all existed since forever but the library did not distinguish them and did not provide prefix information for users to tell which had been decoded.
2026-05-25adapt long-mode behavior support to protected mode and real modeiximeow
along the way, fix an error: maskmov is memory read-write. additionally, operand information about {push,pop}a{,d}.
2026-05-25gpr register size in real/protected modeiximeow
2026-05-25disallow 66-prefixed sha1rnds4iximeow
2026-05-25pusha/popa/push-imm memory sizesiximeow
2026-05-25helpers to create cr0-cr7iximeow
2026-05-25working through a bunch of avx512 stuff, regspec constructors are constiximeow
2026-05-25pextr*/extractpsiximeow
2026-05-25report memory access size for "monitor"iximeow
2026-05-25maskmov{q,dqu} memory access sizeiximeow
2026-05-25more precise about 0f0d prefetch/nopiximeow
2026-05-25fix table management instructions' ({l,s}{g,i,l}dt) mem_sizeiximeow
these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know!
2026-05-25push/pop for segment registers has implicit memory accessiximeow
2026-05-25pushf, popf, enter, leave, xlat all have implicit memory accessiximeow
also add "is_masked" to operand spec
2026-05-25add initial stats for disasm stats in all modesiximeow
2026-02-14type aliases make some of these signatures less egregious..iximeow
2025-06-01describe the per-isa extensions a bit betteriximeow
2025-06-01revise_instruction is the same on all bitnesses, so macro it tooiximeow
2025-06-01DecodeEverything wasn't useful, no better than InstDecoder::default()??iximeow
2025-06-01expand isa feature selection to more bitsiximeow
this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory
2024-06-24rename most operand variants, make them structy rather than tupleyiximeow
2024-06-23remove selects_cs(), cs() now does the right thingiximeow
2024-06-23fix several sources of dead code warnings in various crate configsiximeow
2024-06-23remove yaxpeax-x86 safer_unchecked.rs, it is now in yaxpeax-archiximeow
2024-06-23cfg_attr wants feature, not features pluraliximeow
2024-06-23InstructionTextBuffer for all three modes, adjust fuzzer to matchiximeow
2024-06-23adapt OperandVisitor and related to real_modeiximeow
2024-06-23fix AbsoluteFarAddress being tagged as a memory operandiximeow
2024-06-23actually use new can_lock in 32b and 16b modesiximeow
2024-06-23port opcode helpers and reordering to 32-bit and 16-bit decodersiximeow
2024-06-23add more conditional inlining for 32-bit and 16-bit decodersiximeow
2023-12-16fix hreset being disassembled as having second operand of "Nothing"iximeow
just report it having one operand...
2023-07-24fix handling of lar/lsl source registeriximeow
2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-16forward changes along to 16-bit decoder...iximeow