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2023-12-16fix incorrect register selection for `vpmov*2m` with `rex.r` setiximeow
2023-12-16fix incorrect register selection for `vpmovm2*` with `rex.b` setiximeow
2023-12-16abnormal memory sizes for keylocker instructions are not bugsiximeow
new `does_not_decode_invalid_registers` fuzzer found other bugs! the 384-bit accesses for 128b keylocker instructions are an otherwise-unknown size and had a memory size of `BUG`. they are not bugs. give the memory size a real name.
2023-12-16fix opportunity for unhandled register synonymsiximeow
registers `al`, `cl`, `dl`, and `bl` could have two different representations - with `rex.w` and without. these two forms of `RegSpec` would not compare equal, nor has the same, so for code relying on `RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these synonyms would introduce bugs in register analysis. for example, in `yaxpeax-core`, this would result in instructions writing to `rex.w al` not being visible as definitions for a future read of `!rex.w al`. fix this in `x86_64` code, add new test cases about the confusion, adjust register names to make this situation more clearly a bug, and introduce two new fuzz targets that would have helped spot this error.
2023-12-15more RegSpec constructor validation, fix bug in x86_64 1b reg specsiximeow
* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9
2023-12-15fix incorrect register numbers in r12/r13 RegSpec constructor functionsDongjia "toka" Zhang
these functions had a copypaste error where the r12 and r13 versions would create RegSpec for registers 8 and 9 instead of 12 and 13. use correct register numbers in these macros.
2023-07-24fix handling of lar/lsl source registeriximeow
2023-07-23fix inconsistently-poreted memory access size of vcvt{,t}{sd,si}iximeow
2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-16forward changes along to 16-bit decoder...iximeow
2023-07-16fix indentationiximeow
2023-07-16unify 64-/32-bit moreiximeow
2023-07-16forward changes along to 32-bit decoder...iximeow
2023-07-09trying to delete branches on bank sizeiximeow
2023-07-09more matches to be mad at and turn into lookups insteadiximeow
2023-07-09irritated at matchesiximeow
2023-07-09that doesnt need to be a transmuteiximeow
2023-07-09changing OpcodeRecord to avoid bad use of simdiximeow
2023-07-09smaller tables and err variants preserves perf, but less code/dataiximeow
2023-07-09table-izing these matches substantially helps (pending bugs...)iximeow
2023-07-09remove very done todoiximeow
2023-07-09bitpacking is_memory seems to help (surpisingly much!)iximeow
2023-07-09Revert "restructuring of hotpath code, not worse but not better"iximeow
This reverts commit 15c821a2d3fbf2fc0458090b6cc12f2ac093f075.
2023-07-09restructuring of hotpath code, not worse but not betteriximeow
2023-07-08consistently report end of prefixes/start of opcodeiximeow
2023-07-08todo for 2.xiximeow
2023-07-08seems like this makes things a bit faster...?iximeow
2023-07-08move rip-rel check to a slightly colder spot...iximeow
2023-07-08actually reject lock prefixes in vex instructionsiximeow
2023-07-08fix v(p)gather situations, get vex tests passing againiximeow
2023-07-06defer assigning mem_size or operand_count tooiximeow
2023-07-06M_Gv should be unreachable too...iximeow
2023-07-06defer initial assignment of regs and operands as much as possibleiximeow
not a huge improvement, but something
2023-07-05fix operand handling for the psl/psr family of xmm shifts/rotatesiximeow
these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed)
2023-07-05re-correct operand order of movdq2qiximeow
2023-07-04more read_E hoistingiximeow
2023-07-04incidental cleanup, see if inlining in evex helps/hurts (it hurts)iximeow
2023-07-04fix xbegin/xend (broken in DecodeCtx::rrr)iximeow
2023-07-04finally delete top-level modrm (50.10cpi, 2322ms)iximeow
2023-07-04begin project to hoist all read_E (perf better again! 50.21cpi)iximeow
2023-07-04fix f6 test imm lengths (perf regression :( )iximeow
2023-07-04new high score 49.89cpi (2259ms)iximeow
vex/rex prefix cleanup, finally profitable to inline read_0f*_opcode
2023-07-04more read_E cleanupiximeow
2023-07-04new struct for temporary decode context (prefix management)iximeow
2023-07-04new record: 50.56cpi (2290ms)iximeow
2023-07-04new perf record: 50.79cpi (2316ms)iximeow
2023-07-04best: 54.3cpi (2512ms)iximeow
2023-07-04new perf record: 51.88cpi (2363ms)iximeow
2023-07-04wipiximeow
2023-07-04more micro-opts...iximeow
set_embedded_instructions was unnecessarily appilied to many operand codes; this was never a correctness issue, but meant many operand decodings took a few more instruction than necessary to do nothing. setting all registers to `rax` is unnecessary, only the first register's defaulting to `rax` is effectual. this allows for not using a movabs to load initial rax state. adjust vex decoder inlining. this will be followed up by some cleanup for vex operand codes.
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