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13 daysfix jrcxz/jecxz/jcxz having "two operands"iximeow
2026-05-25push/pop width in 16/32-bit modes are receptive to operand width prefixiximeow
2026-05-25reject arpl in 16-bit decodingiximeow
2026-05-25and some prefix helpers should be pubiximeow
2026-05-25j*cxz/pusha/popa alternate size formsiximeow
2026-05-25adapt long-mode behavior support to protected mode and real modeiximeow
2026-05-25add behavior information for x86_64 instructionsiximeow
2026-05-25gpr register size in real/protected modeiximeow
2026-05-25disallow 66-prefixed sha1rnds4iximeow
2026-05-25pusha/popa/push-imm memory sizesiximeow
2026-05-25helpers to create cr0-cr7iximeow
2026-05-25working through a bunch of avx512 stuff, regspec constructors are constiximeow
2026-05-25pextr*/extractpsiximeow
2026-05-25feature guard for key lockeriximeow
2026-05-25invept precisioniximeow
2026-05-25more precision for vinsert/vextract/vblendv{ps,pd}iximeow
2026-05-25actually support avx/f16c in per-uarch decodingiximeow
2026-05-25vmaskmovdqu, vmovq were also incorrect in some ways...iximeow
2026-05-25more general avx improvementsiximeow
2026-05-25cleanup pass on vex-encoded instructions is going to be excitingiximeow
2026-05-25report memory access size for "monitor"iximeow
2026-05-25maskmov{q,dqu} memory access sizeiximeow
2026-05-25more precise about 0f0d prefetch/nopiximeow
2026-05-25fix table management instructions' ({l,s}{g,i,l}dt) mem_sizeiximeow
2026-05-25more accurate mov seg-to-gpr operand sizeiximeow
2026-05-25push/pop for segment registers has implicit memory accessiximeow
2026-05-25pushf, popf, enter, leave, xlat all have implicit memory accessiximeow
2026-05-25add initial stats for disasm stats in all modesiximeow
2026-02-22correct push-immediate memory access sizeiximeow
2026-02-14fair enough on those warningsiximeow
2026-02-14type aliases make some of these signatures less egregious..iximeow
2026-02-14uarch settings for apx, avx10.1, etc + nouns get capsiximeow
2025-06-013dnow was still supported on K8, K10. 32-bit mode should learn about uarch tw...iximeow
2025-06-01describe the per-isa extensions a bit betteriximeow
2025-06-01revise_instruction is the same on all bitnesses, so macro it tooiximeow
2025-06-01DecodeEverything wasn't useful, no better than InstDecoder::default()??iximeow
2025-06-01cpu feature bits are the same across 64/32/16-bitiximeow
2025-06-01expand isa feature selection to more bitsiximeow
2024-06-24document one more stray unsafeiximeow
2024-06-24justify the current max instruction lengthiximeow
2024-06-24consistently enter register/number/opcode spansiximeow
2024-06-24one more stray docs erroriximeow
2024-06-24rename most operand variants, make them structy rather than tupleyiximeow
2024-06-23remove selects_cs(), cs() now does the right thingiximeow
2024-06-23nightly correctly remarked that == on fat pointers is ambiguousiximeow
2024-06-23fix several sources of dead code warnings in various crate configsiximeow
2024-06-23remove yaxpeax-x86 safer_unchecked.rs, it is now in yaxpeax-archiximeow
2024-06-23cfg_attr wants feature, not features pluraliximeow
2024-06-23last vestiges of initial perf experimentsiximeow
2024-06-23another fuzz bugiximeow