| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 31 hours | push/pop width in 16/32-bit modes are receptive to operand width prefix | iximeow | |
| 32 hours | reject arpl in 16-bit decoding | iximeow | |
| 32 hours | and some prefix helpers should be pub | iximeow | |
| 32 hours | j*cxz/pusha/popa alternate size forms | iximeow | |
| these all existed since forever but the library did not distinguish them and did not provide prefix information for users to tell which had been decoded. | |||
| 44 hours | adapt long-mode behavior support to protected mode and real mode | iximeow | |
| along the way, fix an error: maskmov is memory read-write. additionally, operand information about {push,pop}a{,d}. | |||
| 46 hours | add behavior information for x86_64 instructions | iximeow | |
| this is a squash of a few months' hacking, including but not limited to what eventually got extracted into https://git.iximeow.net/asmlinator/about/ the path here is generally not historically interesting, and the vast majority of this diff is very particular static data tables (BehaviorDigests and implicit operand lists) `src/long_mode/behavior.rs` will more or less be directly adapted into versions for x86-32 and x86-16, similar to the instruction decoders. | |||
| 2 days | gpr register size in real/protected mode | iximeow | |
| 2 days | disallow 66-prefixed sha1rnds4 | iximeow | |
| 2 days | pusha/popa/push-imm memory sizes | iximeow | |
| 2 days | helpers to create cr0-cr7 | iximeow | |
| 2 days | working through a bunch of avx512 stuff, regspec constructors are const | iximeow | |
| 2 days | pextr*/extractps | iximeow | |
| 2 days | feature guard for key locker | iximeow | |
| 2 days | invept precision | iximeow | |
| 2 days | more precision for vinsert/vextract/vblendv{ps,pd} | iximeow | |
| 2 days | actually support avx/f16c in per-uarch decoding | iximeow | |
| 2 days | vmaskmovdqu, vmovq were also incorrect in some ways... | iximeow | |
| 2 days | more general avx improvements | iximeow | |
| 2 days | cleanup pass on vex-encoded instructions is going to be exciting | iximeow | |
| 2 days | report memory access size for "monitor" | iximeow | |
| 2 days | maskmov{q,dqu} memory access size | iximeow | |
| 2 days | more precise about 0f0d prefetch/nop | iximeow | |
| 2 days | fix table management instructions' ({l,s}{g,i,l}dt) mem_size | iximeow | |
| these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know! | |||
| 2 days | more accurate mov seg-to-gpr operand size | iximeow | |
| 2 days | push/pop for segment registers has implicit memory access | iximeow | |
| 2 days | pushf, popf, enter, leave, xlat all have implicit memory access | iximeow | |
| also add "is_masked" to operand spec | |||
| 2 days | add initial stats for disasm stats in all modes | iximeow | |
| 2026-02-22 | correct push-immediate memory access size | iximeow | |
| 2026-02-14 | fair enough on those warnings | iximeow | |
| 2026-02-14 | type aliases make some of these signatures less egregious.. | iximeow | |
| 2026-02-14 | uarch settings for apx, avx10.1, etc + nouns get caps | iximeow | |
| 2025-06-01 | 3dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵ | iximeow | |
| tweaks too | |||
| 2025-06-01 | describe the per-isa extensions a bit better | iximeow | |
| 2025-06-01 | revise_instruction is the same on all bitnesses, so macro it too | iximeow | |
| 2025-06-01 | DecodeEverything wasn't useful, no better than InstDecoder::default()?? | iximeow | |
| 2025-06-01 | cpu feature bits are the same across 64/32/16-bit | iximeow | |
| 2025-06-01 | expand isa feature selection to more bits | iximeow | |
| this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory | |||
| 2024-06-24 | document one more stray unsafe | iximeow | |
| 2024-06-24 | justify the current max instruction length | iximeow | |
| this is also checked by a new fuzz target | |||
| 2024-06-24 | consistently enter register/number/opcode spans | iximeow | |
| 2024-06-24 | one more stray docs error | iximeow | |
| 2024-06-24 | rename most operand variants, make them structy rather than tupley | iximeow | |
| 2024-06-23 | remove selects_cs(), cs() now does the right thing | iximeow | |
| 2024-06-23 | nightly correctly remarked that == on fat pointers is ambiguous | iximeow | |
| 2024-06-23 | fix several sources of dead code warnings in various crate configs | iximeow | |
| 2024-06-23 | remove yaxpeax-x86 safer_unchecked.rs, it is now in yaxpeax-arch | iximeow | |
| 2024-06-23 | cfg_attr wants feature, not features plural | iximeow | |
| 2024-06-23 | last vestiges of initial perf experiments | iximeow | |
| 2024-06-23 | another fuzz bug | iximeow | |
| 2024-06-23 | fuzz caught negation bug | iximeow | |
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index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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