| Age | Commit message (Expand) | Author |
|---|
| 5 days | adjust test framework to support complex ops, some other cleanup | iximeow |
| 6 days | behavior feature, also shrink 40kb from behavior additions | iximeow |
| 6 days | so much more docs | iximeow |
| 6 days | warning fix | iximeow |
| 9 days | add behavior fuzzing, fix some stuff it noticed | iximeow |
| 11 days | the rest of x86-64 behaviors. so far. | iximeow |
| 11 days | even more EVEX encoding precision, regspec constructors are const | iximeow |
| 2026-05-08 | vex support done, starting on evex.. | iximeow |
| 2026-05-08 | working through a bunch of avx512 stuff.. | iximeow |
| 2026-05-04 | pextr*/extractps | iximeow |
| 2026-05-04 | feature guard for key locker | iximeow |
| 2026-05-03 | invept precision | iximeow |
| 2026-05-03 | vblendv{ps,pd} precision | iximeow |
| 2026-05-03 | more precision for vinsert/vextract | iximeow |
| 2026-05-03 | actually support avx/f16c in per-uarch decoding | iximeow |
| 2026-05-03 | much closer to comprehensively covering vex instructions.. | iximeow |
| 2026-05-02 | vmaskmovdqu, vmovq were also incorrect in some ways... | iximeow |
| 2026-04-30 | more general avx improvements | iximeow |
| 2026-04-23 | start verifying vex-encoded instruction behavior | iximeow |
| 2026-04-23 | cleanup pass on vex-encoded instructions is going to be exciting | iximeow |
| 2026-04-19 | report memory access size for "monitor" | iximeow |
| 2026-04-19 | a few more straggler instructions | iximeow |
| 2026-04-19 | the rest of sse? | iximeow |
| 2026-04-19 | substantially more sse coverage | iximeow |
| 2026-04-17 | TODO: 32/16, maskmov{q,dqu} memory access size | iximeow |
| 2026-04-17 | more precise about 0f0d prefetch/nop | iximeow |
| 2026-04-12 | cmovcc: encode operand 2 correctly | iximeow |
| 2026-04-12 | check and support more 0fXX opcodes | iximeow |
| 2026-04-12 | test table management instructions ({l,s}{g,i,l}dt) | iximeow |
| 2026-04-12 | many conditional instructions, jump, call, and start testing 0f opcodes | iximeow |
| 2026-03-28 | more behavior, the rest of two-byte instructions? | iximeow |
| 2026-03-27 | more accurate mov seg-to-gpr operand size | iximeow |
| 2026-03-27 | push/pop for segment registers has implicit memory access | iximeow |
| 2026-03-27 | div ops, mul ops, some other | iximeow |
| 2026-03-19 | more instructions, figured out mul/imul | iximeow |
| 2026-03-09 | back at it with more instruction behaviors and carveouts | iximeow |
| 2026-03-09 | separate: more implicit operand size bits | iximeow |
| 2026-03-09 | api and more inst behavior | iximeow |
| 2026-03-09 | write/read writes operand 0 | iximeow |
| 2026-03-09 | exception vector fmt | iximeow |
| 2026-03-02 | this might actually work omggggg | iximeow |
| 2026-02-25 | hey that's useful | iximeow |
| 2026-02-23 | more expansive access behavior validation, start on implicit op lists | iximeow |
| 2026-02-23 | visit flags changes, tests caught a bug! | iximeow |
| 2026-02-23 | draft | iximeow |
| 2026-02-22 | correct push-immediate memory access sizeHEADno-gods-no- | iximeow |
| 2026-02-14 | fair enough on those warnings | iximeow |
| 2026-02-14 | type aliases make some of these signatures less egregious.. | iximeow |
| 2026-02-14 | uarch settings for apx, avx10.1, etc + nouns get caps | iximeow |
| 2025-06-01 | 3dnow was still supported on K8, K10. 32-bit mode should learn about uarch tw... | iximeow |
