Age | Commit message (Collapse) | Author |
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add `OperandCodeBuilder` to help manage allocation of enum variant
values, since bit patterns of `OperandCode` are very load-bearing for
decoding
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deduplicate and move displacement reading
make Invalid discriminant 0 to simplify "is invalid" checks (test reg, reg instead of cmp reg, imm)
pad out Prefixes to 32-bits (theory being that prefix copying is now one mov instead of two)
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add tests for modrm/sib decoding, xsave extensions
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additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
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also add builders to get decoders appropriate for specific
microarchitectures from intel and amd
* low-power architectures are not yet present
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this is largely wrong for memory operands, which require more invasive changes
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avx is still incomplete, but less so
avx is still practically untested
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also support vmxon to finish out the f30f opcode map
add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't
provide a way to distinguish different operand sizes (yet)
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largely f20f/f30f opcode map items
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this isn't quite all of sse2, but gets close. the f20f opcode map still
needs some touching up.
also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand
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this makes these usable as keys in collections such as BTreeMap. there
is no specific ordering imposed by Ord (f.ex it may be the case that
`eax > dx` while `eax > rax`), but some specific ordering may be imposed
in the future.
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it depended on crates that dragged in std, oops
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really need to adjust OperandCode, almost out of one-off options...
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this adds in some missing sse2 instructions in the alternate secondary
opcode map. because these were missing, instructions were incorrectly
decoded from the 0f opcode map, yielding mmx-operand versions of
themselves (usually)
there are undoubtedly more missing sse2 instructions from the 660f map.
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this makes yaxpeax-x86 no_std. no externally-visible changes!
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fix several instances of incorrect instruction lengths
* immediates for `mov reg, imm` and some other instructions were double-counted
* lengths for vex prefixes were wrong all over the place
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this assists many misdecodes from being totally wrong to only slightly
wrong and more clear about it (rrr-selected opcodes or W-bit-selected
opcodes were accidentally decoded as the first variant of their opcode)
also fixes sillier warnings all over the place, and probably a few
incorrectly counted lengths
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for hashmaps with heavy traffic keyed on RegSpec, this can be a significant time savings
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this includes respecting ModRM_XXXX-style operand codes from alternate
0f opcode maps. this MAY introduce bugs where an opcode 0fXX is valid
by the 0f map, invalid by the 660f map, and we see a sequence like
660fXXYY. if YY results in 0fXX being invalid by 660f, we may have to
fall back to reading opcode XX as an 0f opcode, where YY needs to be
re-read with the correct operand code.
hopefully this doesn't actually happen...
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