yaxpeax-x86 - yaxpeax x86 decoder

Age	Commit message (Collapse)	Author
2020-05-03	"is there a rep prefix" is something people need to be able to ask	iximeow

2020-05-03	add width() to ask width of an x86 operand	iximeow
	this is largely wrong for memory operands, which require more invasive changes
2020-05-03	that instruction is cwd, not cbd	iximeow

2020-05-03	bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffi	iximeow

2020-03-23	update docs to not be long_mode-specific	iximeow

2020-03-22	bump to 0.0.10 to fix a warning0.0.10	iximeow

2020-03-22	yaxpeax-x86 decodes in 32-bit mode now	iximeow

2020-02-22	explicitly report x87 as not (yet) supported	iximeow

2020-02-22	support most avx operand codes	iximeow
	avx is still incomplete, but less so avx is still practically untested
2020-02-22	fix {jmp,call} <reg>, as well as jmpf/callf	iximeow
	also support vmxon to finish out the f30f opcode map add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't provide a way to distinguish different operand sizes (yet)
2020-02-22	more sse/sse2 support	iximeow
	largely f20f/f30f opcode map items
2020-02-22	support 660f sse2 instructions	iximeow
	this isn't quite all of sse2, but gets close. the f20f opcode map still needs some touching up. also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand
2020-02-16	embarassingly had OperandSpec variants for modrm displacement == 0 backwards	iximeow

2020-02-11	support `in` and `out` instructions	iximeow

2020-02-11	add `RegSpec::name` to get `&'static str` labels for registers	iximeow

2020-02-11	derive Ord and PartialOrd for RegSpec and RegisterBank	iximeow
	this makes these usable as keys in collections such as BTreeMap. there is no specific ordering imposed by Ord (f.ex it may be the case that `eax > dx` while `eax > rax`), but some specific ordering may be imposed in the future.
2020-01-15	support "int imm8" instructions	iximeow

2020-01-15	make space for non-64bit modes	iximeow

2020-01-15	make x86 actually no_std	iximeow
	it depended on crates that dragged in std, oops
2020-01-15	add more sse2 instructions (packed shift by immediate, mostly)	iximeow
	really need to adjust OperandCode, almost out of one-off options...
2020-01-15	add 660f6* series instructions as well as 660f70	iximeow
	this adds in some missing sse2 instructions in the alternate secondary opcode map. because these were missing, instructions were incorrectly decoded from the 0f opcode map, yielding mmx-operand versions of themselves (usually) there are undoubtedly more missing sse2 instructions from the 660f map.
2020-01-15	no_std!!	iximeow
	this makes yaxpeax-x86 no_std. no externally-visible changes!
2020-01-13	explicitly fail to handle WAIT prefix	iximeow

2020-01-13	test that instruction lengths are correct	iximeow
	fix several instances of incorrect instruction lengths * immediates for `mov reg, imm` and some other instructions were double-counted * lengths for vex prefixes were wrong all over the place
2020-01-13	add Default impl for Instruction to track yaxpeax-arch	iximeow

2020-01-13	de-pub some internal functions	iximeow

2020-01-12	no println when decoding vex instructions please	iximeow

2020-01-12	"fix warnings"	iximeow
	this assists many misdecodes from being totally wrong to only slightly wrong and more clear about it (rrr-selected opcodes or W-bit-selected opcodes were accidentally decoded as the first variant of their opcode) also fixes sillier warnings all over the place, and probably a few incorrectly counted lengths
2020-01-12	match changes in arch to have Resulty decode, instead of Option	iximeow

2020-01-12	custom hasher for regspec	iximeow
	for hashmaps with heavy traffic keyed on RegSpec, this can be a significant time savings
2020-01-12	display more directly	iximeow

2020-01-12	avx feature flag and avx/aesni instructions flagged properly	iximeow

2020-01-12	fix avx bit number	iximeow

2020-01-12	support aesni	iximeow
	this includes respecting ModRM_XXXX-style operand codes from alternate 0f opcode maps. this MAY introduce bugs where an opcode 0fXX is valid by the 0f map, invalid by the 660f map, and we see a sequence like 660fXXYY. if YY results in 0fXX being invalid by 660f, we may have to fall back to reading opcode XX as an 0f opcode, where YY needs to be re-read with the correct operand code. hopefully this doesn't actually happen...
2020-01-12	support missing sse3 instructions, add tests for sse3 instructions	iximeow

2020-01-12	add avx decoder flag, and a display impl showing active features	iximeow

2020-01-12	test fence instructions against different quirks modes	iximeow
	add enclv instruction add sse3, ssse3, sse4.1, and sse4.2 feature flags, plus a host of missing opcodes
2020-01-12	initial flagging support	iximeow

2020-01-12	add a slew of system-y instructions, as well as cpu quirks for amd/intel ↵	iximeow
	fence instructions
2020-01-12	vex tests work!	iximeow

2020-01-12	vex	iximeow

2020-01-12	movs on non-byte operands	iximeow

2020-01-12	that wasnt supposed to get committed	iximeow

2020-01-12	proper movs operand support	iximeow

2020-01-12	pshuf/psr/shld/shrd plus some test fixes	iximeow
	this makes all current non-vex/evex tests pass!!!
2020-01-12	down to one failing test, for now	iximeow

2020-01-12	more cvt variants	iximeow

2020-01-12	improved cvts again, movd/movq	iximeow

2020-01-12	add pxor and some others, support mm operands	iximeow

2020-01-12	support ucomiss, cvt*, some other sse instructions	iximeow