aboutsummaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2020-08-09crank up the inlineriximeow
2020-08-09cmc and int1iximeow
2020-08-09invalid instruction fixiximeow
2020-08-09lea speed holeiximeow
2020-08-09speed holesiximeow
2020-08-09vinserti128iximeow
2020-08-09vextractf128iximeow
2020-08-09vpsrlqiximeow
2020-08-09vpminswiximeow
2020-08-09vpermq (avx2)iximeow
2020-08-09vpsrlw avxiximeow
2020-08-09missing avx instriximeow
2020-08-09handle bad leaiximeow
2020-08-09more popiximeow
2020-08-09long instructionsiximeow
2020-08-09loop{,z,nz}/jecxziximeow
2020-08-09movabs/offsetiximeow
2020-08-09correctly handle some more invalid opcode scenariosiximeow
2020-08-09handle bad fe/ff opcode cases betteriximeow
2020-08-09fix setcc decodingiximeow
2020-08-09warnings-b-goniximeow
2020-08-09remove unused OperandCode variantsiximeow
2020-08-09more operand code cleanupiximeow
2020-08-09x87 support, plus several other missing instructionsiximeow
2020-08-09sse4.2 tests and missing instructionsiximeow
2020-08-09sse4.1 instruction testsiximeow
2020-08-09display bits refactoriximeow
2020-08-09probably notiximeow
2020-08-09congratulations on your promotioniximeow
2020-08-09simplify leaiximeow
2020-08-09change it all aroundiximeow
add `OperandCodeBuilder` to help manage allocation of enum variant values, since bit patterns of `OperandCode` are very load-bearing for decoding
2020-07-26decode lahf/sahfiximeow
2020-07-26more inline-friendliness when built without LTOiximeow
2020-07-26make read_num more amenable to inliningiximeow
deduplicate and move displacement reading make Invalid discriminant 0 to simplify "is invalid" checks (test reg, reg instead of cmp reg, imm) pad out Prefixes to 32-bits (theory being that prefix copying is now one mov instead of two)
2020-07-26ptest, pmovzxiximeow
2020-07-26ins/outsiximeow
2020-07-26bitwise ops, test cases, btriximeow
2020-07-26BTR is ev,gv not qiximeow
2020-07-26palignr and mpsabdwiximeow
2020-07-26ssse3, some missing sse4.1, and pextrw operandsiximeow
2020-07-26support upper end of 0f opcode map mmx instructionsiximeow
2020-07-18intel supported cmpxchg16b from the first x86_64 architectureiximeow
2020-05-23fix docs up, fix the spelling of penryn0.0.13iximeow
2020-05-23fix important memory decode error in long modeiximeow
add tests for modrm/sib decoding, xsave extensions
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present
2020-05-03"is there a rep prefix" is something people need to be able to askiximeow
2020-05-03add width() to ask width of an x86 operandiximeow
this is largely wrong for memory operands, which require more invasive changes
2020-05-03that instruction is cwd, not cbdiximeow
2020-05-03bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffiiximeow
generated by cgit v1.1 at 2024-11-05 03:33:57 +0000