| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-12-16 | fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` set | iximeow | |
| 2023-12-16 | fix incorrect register selection for `vpmov*2m` with `rex.r` set | iximeow | |
| 2023-12-16 | fix incorrect register selection for `vpmovm2*` with `rex.b` set | iximeow | |
| 2023-12-16 | abnormal memory sizes for keylocker instructions are not bugs | iximeow | |
| new `does_not_decode_invalid_registers` fuzzer found other bugs! the 384-bit accesses for 128b keylocker instructions are an otherwise-unknown size and had a memory size of `BUG`. they are not bugs. give the memory size a real name. | |||
| 2023-12-16 | fix opportunity for unhandled register synonyms | iximeow | |
| registers `al`, `cl`, `dl`, and `bl` could have two different representations - with `rex.w` and without. these two forms of `RegSpec` would not compare equal, nor has the same, so for code relying on `RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these synonyms would introduce bugs in register analysis. for example, in `yaxpeax-core`, this would result in instructions writing to `rex.w al` not being visible as definitions for a future read of `!rex.w al`. fix this in `x86_64` code, add new test cases about the confusion, adjust register names to make this situation more clearly a bug, and introduce two new fuzz targets that would have helped spot this error. | |||
| 2023-12-15 | more RegSpec constructor validation, fix bug in x86_64 1b reg specs | iximeow | |
| * the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9 | |||
| 2023-07-24 | fix handling of lar/lsl source register | iximeow | |
| 2023-07-23 | fix inconsistently-poreted memory access size of vcvt{,t}{sd,si} | iximeow | |
| 2023-07-23 | fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit) | iximeow | |
| 2023-07-08 | fix v(p)gather situations, get vex tests passing again | iximeow | |
| 2023-07-05 | fix operand handling for the psl/psr family of xmm shifts/rotates | iximeow | |
| these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed) | |||
| 2023-07-04 | two more test cases | iximeow | |
| 2023-07-04 | fix some dancing between bank size and RegisterBank enum values | iximeow | |
| in the process, fixed a decoding bug dealing with a0/a1/a2/a3 movs (respected rex.b when rex.b should have been ignored) this seems to maybe improve runtime ever so slightly, but this is really meant as a cleanup commit more than anything. | |||
| 2023-03-05 | add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpers | iximeow | |
| this request/suggestion comes from [github](https://github.com/iximeow/yaxpeax-x86/issues/29)! thank you! | |||
| 2022-05-01 | add testing setup for field descriptions | iximeow | |
| 2022-04-24 | fix a few issues preventing no-std builds from ... building | iximeow | |
| this includes a `Makefile` that exercises the various crate configs. most annoyingly, several doc comments needed to grow `#[cfg(feature="fmt")]` blocks so docs continue to build with that feature enabled or disabled. carved out a way to run exhaustive tests; they should be written as `#[ignore]`, and then the makefile will run even ignored tests on the expectation that this will run the exhaustive (but slower) suite. exhaustive tests are not yet written. they'll probably involve spanning 4 byte sequences from 0 to 2^32-1. | |||
| 2021-12-19 | fix incorrect memory size for f30f1e-style nop | iximeow | |
| not only did the instruction have wrong data, but if displayed, the formatter would panic. | |||
| 2021-12-19 | test that invalid RegSpec constructions panic as expected | iximeow | |
| in the process, fix 64-bit rex-byte limit, 32/16-bit mode mask reg limit | |||
| 2021-12-17 | do not panic on negative compressed displacements, i mean it!! | iximeow | |
| 2021-12-16 | displacements are stored as unsigned, but are functionally signed ints | iximeow | |
| so multiplying to expand EVEX compressed offsets can overflow, and that needs to be okay. | |||
| 2021-10-10 | support endbr{32,64} | iximeow | |
| 2021-08-21 | fix negative relative branches (again!!! +- is bad!!!) | iximeow | |
| 2021-08-21 | fix incorrect decoding of 0x9*-series instructions with rex.b | iximeow | |
| 2021-08-14 | relative branches should be shown as $+offset, not just plain offset | iximeow | |
| while x86 branches of immediates are all relative to PC, other architectures may have absolute branches to immediate addresses, leaving this syntax ambiguous and potentially confusing. yaxpeax prefers to write relative offsets `$+...` as a rule, so uphold that here. | |||
| 2021-07-22 | fix incorrect decodes with scas and 67-prefixes1.0.4 | iximeow | |
| 2021-07-04 | support vpscatter{dd,dq,qd,qq} | iximeow | |
| 2021-07-04 | support avx512 registers >=16 | iximeow | |
| 2021-07-04 | handle vzeroupper/vzeroall, reject vzero* with nonzero vvvv | iximeow | |
| 2021-07-04 | support xacquire/xrelease prefixing | iximeow | |
| 2021-07-04 | fix several incorrect tests and docs in 64- and 32-bit modes | iximeow | |
| 2021-07-03 | more carefully test mmx operand sizes | iximeow | |
| 2021-07-03 | be more strict about denying invalid operands | iximeow | |
| 2021-07-03 | support AMD `sev_snp` | iximeow | |
| 2021-07-03 | instructions with evex-coded registers may have registers other than 0 | iximeow | |
| 2021-07-03 | enforce reserved evex prefix bits | iximeow | |
| 2021-07-03 | add hreset | iximeow | |
| 2021-07-03 | support pconfig/tme | iximeow | |
| 2021-07-01 | reallocate OperandCode, convert disparate registers to array | iximeow | |
| also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode. | |||
| 2021-06-27 | add randomized testing against incorrect data in reused instructions | iximeow | |
| 2021-06-27 | all tests now passing for long mode | iximeow | |
| 2021-06-27 | report memory sizes for all long-mode instructions | iximeow | |
| 2021-06-26 | add long-mode avx512 support, except for compressed displacements | iximeow | |
| 2021-06-12 | finish up long mode avx2 | iximeow | |
| 2021-06-11 | add extensive avx and initial avx2 tests, fix several bugs and missing ↵ | iximeow | |
| instructions | |||
| 2021-03-21 | add tsxldtrk | iximeow | |
| does intel know no bounds | |||
| 2021-03-21 | xed says setssbsy and saveprevssp are more permissive | iximeow | |
| 2021-03-21 | add missing vpmaxuw, remove nonsense avx mov | iximeow | |
| 2021-03-21 | complete CET support, add UINTR, add missing VORP{S,D}, other cleanup | iximeow | |
| 2021-03-21 | add waitpkg, clean up unused values, old comments | iximeow | |
| 2021-03-21 | add tdx | iximeow | |
| decoder flag to come | |||
 |
index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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