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path: root/test/long_mode/mod.rs
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2023-12-16abnormal memory sizes for keylocker instructions are not bugsiximeow
new `does_not_decode_invalid_registers` fuzzer found other bugs! the 384-bit accesses for 128b keylocker instructions are an otherwise-unknown size and had a memory size of `BUG`. they are not bugs. give the memory size a real name.
2023-12-16fix opportunity for unhandled register synonymsiximeow
registers `al`, `cl`, `dl`, and `bl` could have two different representations - with `rex.w` and without. these two forms of `RegSpec` would not compare equal, nor has the same, so for code relying on `RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these synonyms would introduce bugs in register analysis. for example, in `yaxpeax-core`, this would result in instructions writing to `rex.w al` not being visible as definitions for a future read of `!rex.w al`. fix this in `x86_64` code, add new test cases about the confusion, adjust register names to make this situation more clearly a bug, and introduce two new fuzz targets that would have helped spot this error.
2023-12-15more RegSpec constructor validation, fix bug in x86_64 1b reg specsiximeow
* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9
2023-07-24fix handling of lar/lsl source registeriximeow
2023-07-23fix inconsistently-poreted memory access size of vcvt{,t}{sd,si}iximeow
2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-08fix v(p)gather situations, get vex tests passing againiximeow
2023-07-05fix operand handling for the psl/psr family of xmm shifts/rotatesiximeow
these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed)
2023-07-04two more test casesiximeow
2023-07-04fix some dancing between bank size and RegisterBank enum valuesiximeow
in the process, fixed a decoding bug dealing with a0/a1/a2/a3 movs (respected rex.b when rex.b should have been ignored) this seems to maybe improve runtime ever so slightly, but this is really meant as a cleanup commit more than anything.
2023-03-05add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpersiximeow
this request/suggestion comes from [github](https://github.com/iximeow/yaxpeax-x86/issues/29)! thank you!
2022-05-01add testing setup for field descriptionsiximeow
2022-04-24fix a few issues preventing no-std builds from ... buildingiximeow
this includes a `Makefile` that exercises the various crate configs. most annoyingly, several doc comments needed to grow `#[cfg(feature="fmt")]` blocks so docs continue to build with that feature enabled or disabled. carved out a way to run exhaustive tests; they should be written as `#[ignore]`, and then the makefile will run even ignored tests on the expectation that this will run the exhaustive (but slower) suite. exhaustive tests are not yet written. they'll probably involve spanning 4 byte sequences from 0 to 2^32-1.
2021-12-19fix incorrect memory size for f30f1e-style nopiximeow
not only did the instruction have wrong data, but if displayed, the formatter would panic.
2021-12-19test that invalid RegSpec constructions panic as expectediximeow
in the process, fix 64-bit rex-byte limit, 32/16-bit mode mask reg limit
2021-12-17do not panic on negative compressed displacements, i mean it!!iximeow
2021-12-16displacements are stored as unsigned, but are functionally signed intsiximeow
so multiplying to expand EVEX compressed offsets can overflow, and that needs to be okay.
2021-10-10support endbr{32,64}iximeow
2021-08-21fix negative relative branches (again!!! +- is bad!!!)iximeow
2021-08-21fix incorrect decoding of 0x9*-series instructions with rex.biximeow
2021-08-14relative branches should be shown as $+offset, not just plain offsetiximeow
while x86 branches of immediates are all relative to PC, other architectures may have absolute branches to immediate addresses, leaving this syntax ambiguous and potentially confusing. yaxpeax prefers to write relative offsets `$+...` as a rule, so uphold that here.
2021-07-22fix incorrect decodes with scas and 67-prefixes1.0.4iximeow
2021-07-04support vpscatter{dd,dq,qd,qq}iximeow
2021-07-04support avx512 registers >=16iximeow
2021-07-04handle vzeroupper/vzeroall, reject vzero* with nonzero vvvviximeow
2021-07-04support xacquire/xrelease prefixingiximeow
2021-07-04fix several incorrect tests and docs in 64- and 32-bit modesiximeow
2021-07-03more carefully test mmx operand sizesiximeow
2021-07-03be more strict about denying invalid operandsiximeow
2021-07-03support AMD `sev_snp`iximeow
2021-07-03instructions with evex-coded registers may have registers other than 0iximeow
2021-07-03enforce reserved evex prefix bitsiximeow
2021-07-03add hresetiximeow
2021-07-03support pconfig/tmeiximeow
2021-07-01reallocate OperandCode, convert disparate registers to arrayiximeow
also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode.
2021-06-27add randomized testing against incorrect data in reused instructionsiximeow
2021-06-27all tests now passing for long modeiximeow
2021-06-27report memory sizes for all long-mode instructionsiximeow
2021-06-26add long-mode avx512 support, except for compressed displacementsiximeow
2021-06-12finish up long mode avx2iximeow
2021-06-11add extensive avx and initial avx2 tests, fix several bugs and missing ↵iximeow
instructions
2021-03-21add tsxldtrkiximeow
does intel know no bounds
2021-03-21xed says setssbsy and saveprevssp are more permissiveiximeow
2021-03-21add missing vpmaxuw, remove nonsense avx moviximeow
2021-03-21complete CET support, add UINTR, add missing VORP{S,D}, other cleanupiximeow
2021-03-21add waitpkg, clean up unused values, old commentsiximeow
2021-03-21add tdxiximeow
decoder flag to come
2021-03-21rewrite 0f-based instruction handlingiximeow
this is... a more significant rewrite than i expected yaxpeax-x86 to ever need. it turns out that capstone is extremely permissive about duplicative 66/f2/f3 prefixes to the point that the implemented prefex handling was unsalvageable. while this replaces the *0f* opcode tables, i haven't profiled these changes. it's possible this is a net improvement for single-byte opcodes, it could be a net loss. code size may be severely impacted. there is still work to do. but this in total gets very close to iced/xed/zydis parity, far more than before. also adds several small extensions, gfni, 3dnow, enqcmd, invpcid, some of cet, and a few missing avx instructions.
2021-03-17support several new extensions, 3dnow, and nuance in invalid operandsiximeow
2021-03-14alternate display mode for c-style expressionsiximeow