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path: root/test/long_mode/mod.rs
AgeCommit message (Expand)Author
2024-06-22extract reusable display bits into yaxpeax-arch, add a visitor fn to Operandiximeow
2024-06-21things compile again, add a few more caution signs around InstructionTextBufferiximeow
2024-06-20starting to get new DisplaySink stuff ready to extract...iximeow
2024-06-19better testing for alternate sinks, fix hex formatting bug....iximeow
2024-06-18enough infratructure to avoid bounds checks, at incredible user costiximeow
2024-06-16commit unshippable wildly unsafe asm-filled printing codeiximeow
2024-04-02display opt: mem size labels and minor segment reporting changesiximeow
2023-12-16fix hreset being disassembled as having second operand of "Nothing"iximeow
2023-12-16fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` setiximeow
2023-12-16fix incorrect register selection for `vpmov*2m` with `rex.r` setiximeow
2023-12-16fix incorrect register selection for `vpmovm2*` with `rex.b` setiximeow
2023-12-16abnormal memory sizes for keylocker instructions are not bugsiximeow
2023-12-16fix opportunity for unhandled register synonymsiximeow
2023-12-15more RegSpec constructor validation, fix bug in x86_64 1b reg specsiximeow
2023-07-24fix handling of lar/lsl source registeriximeow
2023-07-23fix inconsistently-poreted memory access size of vcvt{,t}{sd,si}iximeow
2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-08fix v(p)gather situations, get vex tests passing againiximeow
2023-07-05fix operand handling for the psl/psr family of xmm shifts/rotatesiximeow
2023-07-04two more test casesiximeow
2023-07-04fix some dancing between bank size and RegisterBank enum valuesiximeow
2023-03-05add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpersiximeow
2022-05-01add testing setup for field descriptionsiximeow
2022-04-24fix a few issues preventing no-std builds from ... buildingiximeow
2021-12-19fix incorrect memory size for f30f1e-style nopiximeow
2021-12-19test that invalid RegSpec constructions panic as expectediximeow
2021-12-17do not panic on negative compressed displacements, i mean it!!iximeow
2021-12-16displacements are stored as unsigned, but are functionally signed intsiximeow
2021-10-10support endbr{32,64}iximeow
2021-08-21fix negative relative branches (again!!! +- is bad!!!)iximeow
2021-08-21fix incorrect decoding of 0x9*-series instructions with rex.biximeow
2021-08-14relative branches should be shown as $+offset, not just plain offsetiximeow
2021-07-22fix incorrect decodes with scas and 67-prefixes1.0.4iximeow
2021-07-04support vpscatter{dd,dq,qd,qq}iximeow
2021-07-04support avx512 registers >=16iximeow
2021-07-04handle vzeroupper/vzeroall, reject vzero* with nonzero vvvviximeow
2021-07-04support xacquire/xrelease prefixingiximeow
2021-07-04fix several incorrect tests and docs in 64- and 32-bit modesiximeow
2021-07-03more carefully test mmx operand sizesiximeow
2021-07-03be more strict about denying invalid operandsiximeow
2021-07-03support AMD `sev_snp`iximeow
2021-07-03instructions with evex-coded registers may have registers other than 0iximeow
2021-07-03enforce reserved evex prefix bitsiximeow
2021-07-03add hresetiximeow
2021-07-03support pconfig/tmeiximeow
2021-07-01reallocate OperandCode, convert disparate registers to arrayiximeow
2021-06-27add randomized testing against incorrect data in reused instructionsiximeow
2021-06-27all tests now passing for long modeiximeow
2021-06-27report memory sizes for all long-mode instructionsiximeow
2021-06-26add long-mode avx512 support, except for compressed displacementsiximeow