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path: root/test/long_mode/mod.rs
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2021-12-17do not panic on negative compressed displacements, i mean it!!iximeow
2021-12-16displacements are stored as unsigned, but are functionally signed intsiximeow
so multiplying to expand EVEX compressed offsets can overflow, and that needs to be okay.
2021-10-10support endbr{32,64}iximeow
2021-08-21fix negative relative branches (again!!! +- is bad!!!)iximeow
2021-08-21fix incorrect decoding of 0x9*-series instructions with rex.biximeow
2021-08-14relative branches should be shown as $+offset, not just plain offsetiximeow
while x86 branches of immediates are all relative to PC, other architectures may have absolute branches to immediate addresses, leaving this syntax ambiguous and potentially confusing. yaxpeax prefers to write relative offsets `$+...` as a rule, so uphold that here.
2021-07-22fix incorrect decodes with scas and 67-prefixes1.0.4iximeow
2021-07-04support vpscatter{dd,dq,qd,qq}iximeow
2021-07-04support avx512 registers >=16iximeow
2021-07-04handle vzeroupper/vzeroall, reject vzero* with nonzero vvvviximeow
2021-07-04support xacquire/xrelease prefixingiximeow
2021-07-04fix several incorrect tests and docs in 64- and 32-bit modesiximeow
2021-07-03more carefully test mmx operand sizesiximeow
2021-07-03be more strict about denying invalid operandsiximeow
2021-07-03support AMD `sev_snp`iximeow
2021-07-03instructions with evex-coded registers may have registers other than 0iximeow
2021-07-03enforce reserved evex prefix bitsiximeow
2021-07-03add hresetiximeow
2021-07-03support pconfig/tmeiximeow
2021-07-01reallocate OperandCode, convert disparate registers to arrayiximeow
also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode.
2021-06-27add randomized testing against incorrect data in reused instructionsiximeow
2021-06-27all tests now passing for long modeiximeow
2021-06-27report memory sizes for all long-mode instructionsiximeow
2021-06-26add long-mode avx512 support, except for compressed displacementsiximeow
2021-06-12finish up long mode avx2iximeow
2021-06-11add extensive avx and initial avx2 tests, fix several bugs and missing ↵iximeow
instructions
2021-03-21add tsxldtrkiximeow
does intel know no bounds
2021-03-21xed says setssbsy and saveprevssp are more permissiveiximeow
2021-03-21add missing vpmaxuw, remove nonsense avx moviximeow
2021-03-21complete CET support, add UINTR, add missing VORP{S,D}, other cleanupiximeow
2021-03-21add waitpkg, clean up unused values, old commentsiximeow
2021-03-21add tdxiximeow
decoder flag to come
2021-03-21rewrite 0f-based instruction handlingiximeow
this is... a more significant rewrite than i expected yaxpeax-x86 to ever need. it turns out that capstone is extremely permissive about duplicative 66/f2/f3 prefixes to the point that the implemented prefex handling was unsalvageable. while this replaces the *0f* opcode tables, i haven't profiled these changes. it's possible this is a net improvement for single-byte opcodes, it could be a net loss. code size may be severely impacted. there is still work to do. but this in total gets very close to iced/xed/zydis parity, far more than before. also adds several small extensions, gfni, 3dnow, enqcmd, invpcid, some of cet, and a few missing avx instructions.
2021-03-17support several new extensions, 3dnow, and nuance in invalid operandsiximeow
2021-03-14alternate display mode for c-style expressionsiximeow
2021-01-15support xchg AX/reg0.1.5iximeow
2021-01-15fix several missing or invalid decodings among 0f01 opcodesiximeow
* `mwaitx`, `monitorx`, `rdpru`, and `clzero` are now supported * swapgs is no longer decoded in protected mode * rdpkru and wrpkru are no longer decoded if mod bits != 11
2020-11-19fix decoding of rex-prefixed modrm+sib operands selecting index 0b100 and ↵0.1.4iximeow
base 0b101 for memory operands with a base, index, and displacement either the wrong base would be selected (register number ignored, so only `*ax` or `r8*` would be reported), or yaxpeax-x86 would report a base register is present when it is not (`RegIndexBaseScaleDisp` when the operand is actually `RegScaleDisp`) thank you to Evan Johnson for catching and reporting this bug! also bump crate version to 0.1.4 as this will be immediately tagged and released.
2020-10-27fix misdecode of instructions in opcode 0x800.1.3iximeow
2020-08-09adjust public interface: public items should all be stableiximeow
`OperandCode` (obviously) wildly varies depending on how i feel on a given week, so it's now hidden to avoid people depending on numerical values of its discriminants. `RegisterBank` got a similar treatment with a new `RegisterClass` struct that's suitable for public use.
2020-08-09reject instructions made invalid by lock prefixesiximeow
2020-08-09support salc, get segment register numbers rightiximeow
2020-08-09tests for cltsiximeow
2020-08-09no more incomplete decoder for vex instructionsiximeow
for now
2020-08-09support four-reg operand forms, new testsiximeow
2020-08-09cmc and int1iximeow
2020-08-09vinserti128iximeow
2020-08-09vextractf128iximeow
2020-08-09vpsrlqiximeow
2020-08-09vpminswiximeow