Age | Commit message (Collapse) | Author |
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these instructions had memory sizes reported for the operand, if it was
a memory operand, but for versions with non-memory operands the decoded
`Instruction` would imply that non memory access would happen at all.
now, decoded instructions in these cases will report a more useful
memory size.
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also remove redundant assignments of operand_count and some OperandSpec,
bulk-assign all registers and operands on entry to `read_instr`. this
all, taken together, shaves off about 7 cycles per decode.
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additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
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also add builders to get decoders appropriate for specific
microarchitectures from intel and amd
* low-power architectures are not yet present
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this is largely wrong for memory operands, which require more invasive changes
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