yaxpeax-x86 - yaxpeax x86 decoder

Age	Commit message (Collapse)	Author
2026-04-17	TODO: 32/16, maskmov{q,dqu} memory access size	iximeow

2026-04-12	sgdt/lidt/lgdt test fixes	iximeow

2026-03-27	push/pop for segment registers has implicit memory access	iximeow

2026-03-09	separate: more implicit operand size bits	iximeow

2026-02-22	correct push-immediate memory access sizeHEAD no-gods-no-	iximeow

2024-06-24	rename most operand variants, make them structy rather than tupley	iximeow

2021-08-21	clarify inaccurate 32/16-bit `call/jmp [mem]` mem_size	iximeow

2021-08-21	report memory sizes for push, pop, call, ret	iximeow
	these instructions had memory sizes reported for the operand, if it was a memory operand, but for versions with non-memory operands the decoded `Instruction` would imply that non memory access would happen at all. now, decoded instructions in these cases will report a more useful memory size.
2021-07-03	factor out MemoryAccessSize	iximeow

2021-07-03	add tests for MemoryAccessSize, consistentify style on docs	iximeow

2021-07-01	reallocate OperandCode, convert disparate registers to array	iximeow
	also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode.
2020-05-23	add SHA, BMI1, and BMI2, complete XSAVE extension support	iximeow
	additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
2020-05-21	add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensions	iximeow
	also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present
2020-05-03	add width() to ask width of an x86 operand	iximeow
	this is largely wrong for memory operands, which require more invasive changes