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AgeCommit message (Expand)Author
2021-07-03be more strict about denying invalid operandsiximeow
2021-07-03support AMD `sev_snp`iximeow
2021-07-03clean up x86_32 and make interfaces match x86_64iximeow
2021-07-03add hresetiximeow
2021-07-01[DROP] fix up tests to match newer operand width interfacesiximeow
2021-07-01reallocate OperandCode, convert disparate registers to arrayiximeow
2021-06-28round out x86_32 support - avx2, avx, memory sizesiximeow
2021-06-28protected mode memory sizesiximeow
2021-06-27protected-mode avx512iximeow
2021-03-22port long-mode decoder updates to protected-modeiximeow
2021-03-21update protected mode tests (this breaks them horribly. next commit will fix.)iximeow
2021-01-15support xchg AX/reg0.1.5iximeow
2021-01-15fix several missing or invalid decodings among 0f01 opcodesiximeow
2020-11-19fix decoding of rex-prefixed modrm+sib operands selecting index 0b100 and bas...0.1.4iximeow
2020-10-27fix misdecode of instructions in opcode 0x800.1.3iximeow
2020-08-15add register class constants to allow reasoning about register operands0.1.1iximeow
2020-08-09adjust public interface: public items should all be stableiximeow
2020-08-09reject instructions made invalid by lock prefixesiximeow
2020-08-09support salc, get segment register numbers rightiximeow
2020-08-09tests for cltsiximeow
2020-08-09add 32-bit-only instructionsiximeow
2020-08-09port updates to protected-mode decoderiximeow
2020-08-09update protected mode testsiximeow
2020-05-23fix important memory decode error in long modeiximeow
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
2020-05-03add width() to ask width of an x86 operandiximeow
2020-05-03that instruction is cwd, not cbdiximeow
2020-05-03bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffiiximeow
2020-03-22yaxpeax-x86 decodes in 32-bit mode nowiximeow