| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 13 hours | more general avx improvements | iximeow | |
| 13 hours | cleanup pass on vex-encoded instructions is going to be exciting | iximeow | |
| 13 hours | maskmov{q,dqu} memory access size | iximeow | |
| 13 hours | more precise about 0f0d prefetch/nop | iximeow | |
| 13 hours | fix table management instructions' ({l,s}{g,i,l}dt) mem_size | iximeow | |
| these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know! | |||
| 13 hours | more accurate mov seg-to-gpr operand size | iximeow | |
| 13 hours | push/pop for segment registers has implicit memory access | iximeow | |
| 13 hours | pushf, popf, enter, leave, xlat all have implicit memory access | iximeow | |
| also add "is_masked" to operand spec | |||
| 2025-06-01 | 3dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵ | iximeow | |
| tweaks too | |||
| 2025-06-01 | expand isa feature selection to more bits | iximeow | |
| this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory | |||
| 2024-06-24 | rename most operand variants, make them structy rather than tupley | iximeow | |
| 2024-06-23 | add additional `call` test cases | iximeow | |
| fix 32-bit 66-prefixed ff /2 call not having 16-bit operands fix momentary regression in rendering `call` instructions to string | |||
| 2023-12-16 | fix hreset being disassembled as having second operand of "Nothing" | iximeow | |
| just report it having one operand... | |||
| 2023-12-16 | fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` set | iximeow | |
| 2023-12-16 | fix incorrect register selection for `vpmov*2m` with `rex.r` set | iximeow | |
| 2023-12-16 | fix incorrect register selection for `vpmovm2*` with `rex.b` set | iximeow | |
| 2023-12-16 | abnormal memory sizes for keylocker instructions are not bugs | iximeow | |
| new `does_not_decode_invalid_registers` fuzzer found other bugs! the 384-bit accesses for 128b keylocker instructions are an otherwise-unknown size and had a memory size of `BUG`. they are not bugs. give the memory size a real name. | |||
| 2023-12-15 | more RegSpec constructor validation, fix bug in x86_64 1b reg specs | iximeow | |
| * the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9 | |||
| 2023-07-24 | fix handling of lar/lsl source register | iximeow | |
| 2023-07-23 | fix inconsistently-poreted memory access size of vcvt{,t}{sd,si} | iximeow | |
| 2023-07-16 | forward changes along to 32-bit decoder... | iximeow | |
| 2023-03-05 | add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpers | iximeow | |
| this request/suggestion comes from [github](https://github.com/iximeow/yaxpeax-x86/issues/29)! thank you! | |||
| 2022-04-30 | support 0x9a callf in 16/32-bit modes | iximeow | |
| 2022-04-24 | fix a few issues preventing no-std builds from ... building | iximeow | |
| this includes a `Makefile` that exercises the various crate configs. most annoyingly, several doc comments needed to grow `#[cfg(feature="fmt")]` blocks so docs continue to build with that feature enabled or disabled. carved out a way to run exhaustive tests; they should be written as `#[ignore]`, and then the makefile will run even ignored tests on the expectation that this will run the exhaustive (but slower) suite. exhaustive tests are not yet written. they'll probably involve spanning 4 byte sequences from 0 to 2^32-1. | |||
| 2022-01-12 | fuzz DisplayStyle::C and fix corresponding issues1.1.4 | iximeow | |
| 2021-12-19 | fix incorrect memory size for f30f1e-style nop | iximeow | |
| not only did the instruction have wrong data, but if displayed, the formatter would panic. | |||
| 2021-12-19 | test that invalid RegSpec constructions panic as expected | iximeow | |
| in the process, fix 64-bit rex-byte limit, 32/16-bit mode mask reg limit | |||
| 2021-12-17 | do not panic on negative compressed displacements, i mean it!! | iximeow | |
| 2021-12-16 | displacements are stored as unsigned, but are functionally signed ints | iximeow | |
| so multiplying to expand EVEX compressed offsets can overflow, and that needs to be okay. | |||
| 2021-10-10 | support endbr{32,64} | iximeow | |
| 2021-08-21 | fix negative relative branches (again!!! +- is bad!!!) | iximeow | |
| 2021-08-21 | clarify inaccurate 32/16-bit `call/jmp [mem]` mem_size | iximeow | |
| 2021-08-21 | report memory sizes for push, pop, call, ret | iximeow | |
| these instructions had memory sizes reported for the operand, if it was a memory operand, but for versions with non-memory operands the decoded `Instruction` would imply that non memory access would happen at all. now, decoded instructions in these cases will report a more useful memory size. | |||
| 2021-08-14 | relative branches should be shown as $+offset, not just plain offset | iximeow | |
| while x86 branches of immediates are all relative to PC, other architectures may have absolute branches to immediate addresses, leaving this syntax ambiguous and potentially confusing. yaxpeax prefers to write relative offsets `$+...` as a rule, so uphold that here. | |||
| 2021-07-22 | fix incorrect decodes with scas and 67-prefixes1.0.4 | iximeow | |
| 2021-07-04 | handle vzeroupper/vzeroall, reject vzero* with nonzero vvvv | iximeow | |
| 2021-07-04 | support xacquire/xrelease prefixing | iximeow | |
| 2021-07-04 | fix several incorrect tests and docs in 64- and 32-bit modes | iximeow | |
| 2021-07-03 | update protected_mode to match long_mode docs, apis | iximeow | |
| 2021-07-03 | more carefully test mmx operand sizes | iximeow | |
| 2021-07-03 | factor out MemoryAccessSize | iximeow | |
| 2021-07-03 | add tests for MemoryAccessSize, consistentify style on docs | iximeow | |
| 2021-07-03 | be more strict about denying invalid operands | iximeow | |
| 2021-07-03 | support AMD `sev_snp` | iximeow | |
| 2021-07-03 | clean up x86_32 and make interfaces match x86_64 | iximeow | |
| 2021-07-03 | add hreset | iximeow | |
| 2021-07-01 | [DROP] fix up tests to match newer operand width interfaces | iximeow | |
| 2021-07-01 | reallocate OperandCode, convert disparate registers to array | iximeow | |
| also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode. | |||
| 2021-06-28 | round out x86_32 support - avx2, avx, memory sizes | iximeow | |
| 2021-06-28 | protected mode memory sizes | iximeow | |
| also some long-mode cleanup in corresponding areas | |||
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index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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