aboutsummaryrefslogtreecommitdiff
path: root/test/test.rs
AgeCommit message (Collapse)Author
2020-02-11support `in` and `out` instructionsiximeow
2020-02-11add `RegSpec::name` to get `&'static str` labels for registersiximeow
2020-01-15support "int imm8" instructionsiximeow
2020-01-15make space for non-64bit modesiximeow
2020-01-15add more sse2 instructions (packed shift by immediate, mostly)iximeow
really need to adjust OperandCode, almost out of one-off options...
2020-01-15add 660f6* series instructions as well as 660f70iximeow
this adds in some missing sse2 instructions in the alternate secondary opcode map. because these were missing, instructions were incorrectly decoded from the 0f opcode map, yielding mmx-operand versions of themselves (usually) there are undoubtedly more missing sse2 instructions from the 660f map.
2020-01-15negative displacements were printed wrong, test against that for the futureiximeow
this was accidentally fixed in no_std-ing, the prior commit
2020-01-13explicitly fail to handle WAIT prefixiximeow
2020-01-13test that instruction lengths are correctiximeow
fix several instances of incorrect instruction lengths * immediates for `mov reg, imm` and some other instructions were double-counted * lengths for vex prefixes were wrong all over the place
2020-01-13add Default impl for Instruction to track yaxpeax-archiximeow
2020-01-12"fix warnings"iximeow
this assists many misdecodes from being totally wrong to only slightly wrong and more clear about it (rrr-selected opcodes or W-bit-selected opcodes were accidentally decoded as the first variant of their opcode) also fixes sillier warnings all over the place, and probably a few incorrectly counted lengths
2020-01-12match changes in arch to have Resulty decode, instead of Optioniximeow
2020-01-12avx feature flag and avx/aesni instructions flagged properlyiximeow
2020-01-12support aesniiximeow
this includes respecting ModRM_XXXX-style operand codes from alternate 0f opcode maps. this MAY introduce bugs where an opcode 0fXX is valid by the 0f map, invalid by the 660f map, and we see a sequence like 660fXXYY. if YY results in 0fXX being invalid by 660f, we may have to fall back to reading opcode XX as an 0f opcode, where YY needs to be re-read with the correct operand code. hopefully this doesn't actually happen...
2020-01-12support missing sse3 instructions, add tests for sse3 instructionsiximeow
2020-01-12test fence instructions against different quirks modesiximeow
add enclv instruction add sse3, ssse3, sse4.1, and sse4.2 feature flags, plus a host of missing opcodes
2020-01-12add a slew of system-y instructions, as well as cpu quirks for amd/intel ↵iximeow
fence instructions
2020-01-12vex tests work!iximeow
2020-01-12vexiximeow
2020-01-12proper movs operand supportiximeow
2020-01-12pshuf/psr/shld/shrd plus some test fixesiximeow
this makes all current non-vex/evex tests pass!!!
2020-01-12down to one failing test, for nowiximeow
2020-01-12more cvt variantsiximeow
2020-01-12improved cvts again, movd/movqiximeow
2020-01-12add pxor and some others, support mm operandsiximeow
2020-01-12support ucomiss, cvt*, some other sse instructionsiximeow
2020-01-12more careful prefix handlingiximeow
2020-01-12support prefetch, movlps, movhps, refine prefix permissivityiximeow
rep, repz, repnz prefixes are only displayed on instructions for which they have a semantic effect. movs, cmps, scas, lods, stos, ins, and outs are now decodable.
2020-01-12fix 0x98 and 0x99 opcodes, lss/lfs/lgs decodesiximeow
also remove unnecessary variants in unlikely_operands and adjust expectations of several tests
2020-01-12add display rules for new opcodes, continuing to fix testsiximeow
2020-01-12properly handle excessive prefixes on 0f-category instructioniximeow
also initial support for 660f opcode map, though it's all invalid instructions fix backwards base and index registers for memory operands with both fix incorrect test
2020-01-12hack to handle prefixed sequences that might appear to be escaped opcodesiximeow
2020-01-12support imul, >2 operands, and 4-bit register bankiximeow
2020-01-12most non-avx (really, non-vex) instructionsiximeow
2020-01-12update lar testsiximeow
2020-01-12display impl doesnt show memory operand sizesiximeow
2020-01-12decode shift-by-cl and fix error decoding sign-extending operandsiximeow
2020-01-12mov test casesiximeow
2020-01-12extend prefixed opcode support, add tests for alternate opcode mapsiximeow
2020-01-12add more x86 instructions (bt, btr, bts, bsf, ...) and xaddiximeow
2020-01-12add failing decode test casesiximeow
2020-01-12begin supporting f30f instructionsiximeow
fix issue where non-relevant prefixes on 0f opcodes may cause incorrect invalid decodes
2020-01-12initial support for xmm instructionsiximeow
2020-01-12fix some warnings and rdtsc/swapgs decode errorsiximeow
2020-01-12segment rendering fixesiximeow
2020-01-12starting to get into some system instructions nowiximeow
2020-01-12fix incorrect sign tests and decode odditiesiximeow
2020-01-12several tweaks:iximeow
* DisplacementI32 was never used, DisplacementU64 added to distinguish 8 and 4 byte addresses * Added setCC instructions * Fix sign extension bug for displacement as interpreted by E operands * Add operand code support for a0,a1,a2,a3 movs * Add operand code support for Ivs, Ibs * Complete support for 0x81 * Clean up tests
2020-01-12adjust namespace layoutiximeow
2020-01-12add a vex testiximeow
generated by cgit v1.1 at 2024-11-08 12:06:26 +0000