| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-01-15 | add 660f6* series instructions as well as 660f70 | iximeow | |
| this adds in some missing sse2 instructions in the alternate secondary opcode map. because these were missing, instructions were incorrectly decoded from the 0f opcode map, yielding mmx-operand versions of themselves (usually) there are undoubtedly more missing sse2 instructions from the 660f map. | |||
| 2020-01-15 | negative displacements were printed wrong, test against that for the future | iximeow | |
| this was accidentally fixed in no_std-ing, the prior commit | |||
| 2020-01-13 | explicitly fail to handle WAIT prefix | iximeow | |
| 2020-01-13 | test that instruction lengths are correct | iximeow | |
| fix several instances of incorrect instruction lengths * immediates for `mov reg, imm` and some other instructions were double-counted * lengths for vex prefixes were wrong all over the place | |||
| 2020-01-13 | add Default impl for Instruction to track yaxpeax-arch | iximeow | |
| 2020-01-12 | "fix warnings" | iximeow | |
| this assists many misdecodes from being totally wrong to only slightly wrong and more clear about it (rrr-selected opcodes or W-bit-selected opcodes were accidentally decoded as the first variant of their opcode) also fixes sillier warnings all over the place, and probably a few incorrectly counted lengths | |||
| 2020-01-12 | match changes in arch to have Resulty decode, instead of Option | iximeow | |
| 2020-01-12 | avx feature flag and avx/aesni instructions flagged properly | iximeow | |
| 2020-01-12 | support aesni | iximeow | |
| this includes respecting ModRM_XXXX-style operand codes from alternate 0f opcode maps. this MAY introduce bugs where an opcode 0fXX is valid by the 0f map, invalid by the 660f map, and we see a sequence like 660fXXYY. if YY results in 0fXX being invalid by 660f, we may have to fall back to reading opcode XX as an 0f opcode, where YY needs to be re-read with the correct operand code. hopefully this doesn't actually happen... | |||
| 2020-01-12 | support missing sse3 instructions, add tests for sse3 instructions | iximeow | |
| 2020-01-12 | test fence instructions against different quirks modes | iximeow | |
| add enclv instruction add sse3, ssse3, sse4.1, and sse4.2 feature flags, plus a host of missing opcodes | |||
| 2020-01-12 | add a slew of system-y instructions, as well as cpu quirks for amd/intel ↵ | iximeow | |
| fence instructions | |||
| 2020-01-12 | vex tests work! | iximeow | |
| 2020-01-12 | vex | iximeow | |
| 2020-01-12 | proper movs operand support | iximeow | |
| 2020-01-12 | pshuf/psr/shld/shrd plus some test fixes | iximeow | |
| this makes all current non-vex/evex tests pass!!! | |||
| 2020-01-12 | down to one failing test, for now | iximeow | |
| 2020-01-12 | more cvt variants | iximeow | |
| 2020-01-12 | improved cvts again, movd/movq | iximeow | |
| 2020-01-12 | add pxor and some others, support mm operands | iximeow | |
| 2020-01-12 | support ucomiss, cvt*, some other sse instructions | iximeow | |
| 2020-01-12 | more careful prefix handling | iximeow | |
| 2020-01-12 | support prefetch, movlps, movhps, refine prefix permissivity | iximeow | |
| rep, repz, repnz prefixes are only displayed on instructions for which they have a semantic effect. movs, cmps, scas, lods, stos, ins, and outs are now decodable. | |||
| 2020-01-12 | fix 0x98 and 0x99 opcodes, lss/lfs/lgs decodes | iximeow | |
| also remove unnecessary variants in unlikely_operands and adjust expectations of several tests | |||
| 2020-01-12 | add display rules for new opcodes, continuing to fix tests | iximeow | |
| 2020-01-12 | properly handle excessive prefixes on 0f-category instruction | iximeow | |
| also initial support for 660f opcode map, though it's all invalid instructions fix backwards base and index registers for memory operands with both fix incorrect test | |||
| 2020-01-12 | hack to handle prefixed sequences that might appear to be escaped opcodes | iximeow | |
| 2020-01-12 | support imul, >2 operands, and 4-bit register bank | iximeow | |
| 2020-01-12 | most non-avx (really, non-vex) instructions | iximeow | |
| 2020-01-12 | update lar tests | iximeow | |
| 2020-01-12 | display impl doesnt show memory operand sizes | iximeow | |
| 2020-01-12 | decode shift-by-cl and fix error decoding sign-extending operands | iximeow | |
| 2020-01-12 | mov test cases | iximeow | |
| 2020-01-12 | extend prefixed opcode support, add tests for alternate opcode maps | iximeow | |
| 2020-01-12 | add more x86 instructions (bt, btr, bts, bsf, ...) and xadd | iximeow | |
| 2020-01-12 | add failing decode test cases | iximeow | |
| 2020-01-12 | begin supporting f30f instructions | iximeow | |
| fix issue where non-relevant prefixes on 0f opcodes may cause incorrect invalid decodes | |||
| 2020-01-12 | initial support for xmm instructions | iximeow | |
| 2020-01-12 | fix some warnings and rdtsc/swapgs decode errors | iximeow | |
| 2020-01-12 | segment rendering fixes | iximeow | |
| 2020-01-12 | starting to get into some system instructions now | iximeow | |
| 2020-01-12 | fix incorrect sign tests and decode oddities | iximeow | |
| 2020-01-12 | several tweaks: | iximeow | |
| * DisplacementI32 was never used, DisplacementU64 added to distinguish 8 and 4 byte addresses * Added setCC instructions * Fix sign extension bug for displacement as interpreted by E operands * Add operand code support for a0,a1,a2,a3 movs * Add operand code support for Ivs, Ibs * Complete support for 0x81 * Clean up tests | |||
| 2020-01-12 | adjust namespace layout | iximeow | |
| 2020-01-12 | add a vex test | iximeow | |
| 2020-01-12 | another testcase | iximeow | |
| 2020-01-12 | some more refactoring of RegSpec, support r-b registers, additional test cases | iximeow | |
| 2020-01-12 | add more test cases, fix movzx support, add 0xf6 opcodes | iximeow | |
| 2020-01-12 | initial | iximeow | |
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index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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