aboutsummaryrefslogtreecommitdiff
path: root/test
AgeCommit message (Collapse)Author
2020-08-09reject instructions made invalid by lock prefixesiximeow
2020-08-09support salc, get segment register numbers rightiximeow
2020-08-09tests for cltsiximeow
2020-08-09add 32-bit-only instructionsiximeow
2020-08-09port updates to protected-mode decoderiximeow
2020-08-09update protected mode testsiximeow
2020-08-09no more incomplete decoder for vex instructionsiximeow
for now
2020-08-09support four-reg operand forms, new testsiximeow
2020-08-09cmc and int1iximeow
2020-08-09vinserti128iximeow
2020-08-09vextractf128iximeow
2020-08-09vpsrlqiximeow
2020-08-09vpminswiximeow
2020-08-09vpermq (avx2)iximeow
2020-08-09vpsrlw avxiximeow
2020-08-09handle bad leaiximeow
2020-08-09more popiximeow
2020-08-09long instructionsiximeow
2020-08-09loop{,z,nz}/jecxziximeow
2020-08-09movabs/offsetiximeow
2020-08-09fix setcc decodingiximeow
2020-08-09warnings-b-goniximeow
2020-08-09x87 support, plus several other missing instructionsiximeow
2020-08-09sse4.2 tests and missing instructionsiximeow
2020-08-09sse4.1 instruction testsiximeow
2020-07-26bitwise ops, test cases, btriximeow
2020-07-26ssse3, some missing sse4.1, and pextrw operandsiximeow
2020-07-26support upper end of 0f opcode map mmx instructionsiximeow
2020-05-24fix benchmark bitrotmasteriximeow
2020-05-23fix important memory decode error in long modeiximeow
add tests for modrm/sib decoding, xsave extensions
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present
2020-05-03add width() to ask width of an x86 operandiximeow
this is largely wrong for memory operands, which require more invasive changes
2020-05-03that instruction is cwd, not cbdiximeow
2020-05-03bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffiiximeow
2020-03-22yaxpeax-x86 decodes in 32-bit mode nowiximeow
2020-02-22remove unused functioniximeow
2020-02-22support most avx operand codesiximeow
avx is still incomplete, but less so avx is still practically untested
2020-02-22fix {jmp,call} <reg>, as well as jmpf/callfiximeow
also support vmxon to finish out the f30f opcode map add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't provide a way to distinguish different operand sizes (yet)
2020-02-22more sse/sse2 supportiximeow
largely f20f/f30f opcode map items
2020-02-22add vmclear testiximeow
this instruction is decoded with the sse2 660f map but not actually added in sse2
2020-02-22support 660f sse2 instructionsiximeow
this isn't quite all of sse2, but gets close. the f20f opcode map still needs some touching up. also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand
2020-02-16embarassingly had OperandSpec variants for modrm displacement == 0 backwardsiximeow
2020-02-11support `in` and `out` instructionsiximeow
2020-02-11add `RegSpec::name` to get `&'static str` labels for registersiximeow
2020-01-15support "int imm8" instructionsiximeow
2020-01-15make space for non-64bit modesiximeow
2020-01-15add more sse2 instructions (packed shift by immediate, mostly)iximeow
really need to adjust OperandCode, almost out of one-off options...
2020-01-15add 660f6* series instructions as well as 660f70iximeow
this adds in some missing sse2 instructions in the alternate secondary opcode map. because these were missing, instructions were incorrectly decoded from the 0f opcode map, yielding mmx-operand versions of themselves (usually) there are undoubtedly more missing sse2 instructions from the 660f map.
2020-01-15negative displacements were printed wrong, test against that for the futureiximeow
this was accidentally fixed in no_std-ing, the prior commit
generated by cgit v1.1 at 2024-11-01 07:27:30 +0000