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2020-07-26support upper end of 0f opcode map mmx instructionsiximeow
2020-05-24fix benchmark bitrotmasteriximeow
2020-05-23fix important memory decode error in long modeiximeow
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
2020-05-03add width() to ask width of an x86 operandiximeow
2020-05-03that instruction is cwd, not cbdiximeow
2020-05-03bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffiiximeow
2020-03-22yaxpeax-x86 decodes in 32-bit mode nowiximeow
2020-02-22remove unused functioniximeow
2020-02-22support most avx operand codesiximeow
2020-02-22fix {jmp,call} <reg>, as well as jmpf/callfiximeow
2020-02-22more sse/sse2 supportiximeow
2020-02-22add vmclear testiximeow
2020-02-22support 660f sse2 instructionsiximeow
2020-02-16embarassingly had OperandSpec variants for modrm displacement == 0 backwardsiximeow
2020-02-11support `in` and `out` instructionsiximeow
2020-02-11add `RegSpec::name` to get `&'static str` labels for registersiximeow
2020-01-15support "int imm8" instructionsiximeow
2020-01-15make space for non-64bit modesiximeow
2020-01-15add more sse2 instructions (packed shift by immediate, mostly)iximeow
2020-01-15add 660f6* series instructions as well as 660f70iximeow
2020-01-15negative displacements were printed wrong, test against that for the futureiximeow
2020-01-13explicitly fail to handle WAIT prefixiximeow
2020-01-13test that instruction lengths are correctiximeow
2020-01-13add Default impl for Instruction to track yaxpeax-archiximeow
2020-01-12"fix warnings"iximeow
2020-01-12match changes in arch to have Resulty decode, instead of Optioniximeow
2020-01-12avx feature flag and avx/aesni instructions flagged properlyiximeow
2020-01-12support aesniiximeow
2020-01-12support missing sse3 instructions, add tests for sse3 instructionsiximeow
2020-01-12test fence instructions against different quirks modesiximeow
2020-01-12add a slew of system-y instructions, as well as cpu quirks for amd/intel fenc...iximeow
2020-01-12vex tests work!iximeow
2020-01-12vexiximeow
2020-01-12proper movs operand supportiximeow
2020-01-12pshuf/psr/shld/shrd plus some test fixesiximeow
2020-01-12down to one failing test, for nowiximeow
2020-01-12more cvt variantsiximeow
2020-01-12improved cvts again, movd/movqiximeow
2020-01-12add pxor and some others, support mm operandsiximeow
2020-01-12support ucomiss, cvt*, some other sse instructionsiximeow
2020-01-12more careful prefix handlingiximeow
2020-01-12support prefetch, movlps, movhps, refine prefix permissivityiximeow
2020-01-12fix 0x98 and 0x99 opcodes, lss/lfs/lgs decodesiximeow
2020-01-12add display rules for new opcodes, continuing to fix testsiximeow
2020-01-12properly handle excessive prefixes on 0f-category instructioniximeow
2020-01-12hack to handle prefixed sequences that might appear to be escaped opcodesiximeow
2020-01-12support imul, >2 operands, and 4-bit register bankiximeow
2020-01-12most non-avx (really, non-vex) instructionsiximeow
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