| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 24 hours | add MASM-style formatting support in all modes | iximeow | |
| this includes a mildly nightmarish bit of test harness to compare against ml.exe/ml64.exe/dumpbin.exe, which in turn chased out a bunch of bugs. yay! | |||
| 2026-06-21 | the weird 64b movq thing was a capstone bug all along?! | iximeow | |
| 2026-06-21 | fix several instructions' incorrect memory or op2 size | iximeow | |
| 2026-06-21 | rename rne-sae to rn-sae | iximeow | |
| 2026-06-21 | fix mnemonics for prefetcht* | iximeow | |
| 2026-06-21 | reworking how tests work: more modular now | iximeow | |
| this hopefully gets testcases closer to a point where one could simply write a program that dumps test bytes and expected disassembly. more immediately, this is a structure to dangle an optioanl masm-style disassembly of an instruction for testing that imminent addition too. | |||
| 2026-06-21 | feature gate kvm tests to linux | iximeow | |
| 2026-06-21 | useless use of unsafe | iximeow | |
| 2026-05-25 | push/pop width in 16/32-bit modes are receptive to operand width prefix | iximeow | |
| 2026-05-25 | dont clobber test VM control state in tests.. | iximeow | |
| 2026-05-25 | reject arpl in 16-bit decoding | iximeow | |
| 2026-05-25 | j*cxz/pusha/popa alternate size forms | iximeow | |
| these all existed since forever but the library did not distinguish them and did not provide prefix information for users to tell which had been decoded. | |||
| 2026-05-25 | adapt long-mode behavior support to protected mode and real mode | iximeow | |
| along the way, fix an error: maskmov is memory read-write. additionally, operand information about {push,pop}a{,d}. | |||
| 2026-05-25 | add behavior information for x86_64 instructions | iximeow | |
| this is a squash of a few months' hacking, including but not limited to what eventually got extracted into https://git.iximeow.net/asmlinator/about/ the path here is generally not historically interesting, and the vast majority of this diff is very particular static data tables (BehaviorDigests and implicit operand lists) `src/long_mode/behavior.rs` will more or less be directly adapted into versions for x86-32 and x86-16, similar to the instruction decoders. | |||
| 2026-05-25 | 66-prefixed sha1rnds4 doesnt even real | iximeow | |
| 2026-05-25 | pusha/popa/push-imm memory sizes | iximeow | |
| 2026-05-25 | working through a bunch of avx512 stuff, regspec constructors are const | iximeow | |
| 2026-05-25 | pextr*/extractps | iximeow | |
| 2026-05-25 | invept precision | iximeow | |
| 2026-05-25 | more precision for vinsert/vextract/vblendv{ps,pd} | iximeow | |
| 2026-05-25 | actually support avx/f16c in per-uarch decoding | iximeow | |
| 2026-05-25 | vmaskmovdqu, vmovq were also incorrect in some ways... | iximeow | |
| 2026-05-25 | more general avx improvements | iximeow | |
| 2026-05-25 | cleanup pass on vex-encoded instructions is going to be exciting | iximeow | |
| 2026-05-25 | maskmov{q,dqu} memory access size | iximeow | |
| 2026-05-25 | more precise about 0f0d prefetch/nop | iximeow | |
| 2026-05-25 | fix table management instructions' ({l,s}{g,i,l}dt) mem_size | iximeow | |
| these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know! | |||
| 2026-05-25 | more accurate mov seg-to-gpr operand size | iximeow | |
| 2026-05-25 | push/pop for segment registers has implicit memory access | iximeow | |
| 2026-05-25 | pushf, popf, enter, leave, xlat all have implicit memory access | iximeow | |
| also add "is_masked" to operand spec | |||
| 2026-02-22 | correct push-immediate memory access size | iximeow | |
| 2025-09-29 | fix broken capstone_bench stuff, might delete later, idk | iximeow | |
| 2025-09-29 | annotation description test requires `fmt` | iximeow | |
| this was missed in typical testing because either tests run with all features, no features, or fmt. there wasn't a test entry for only std, which was broken. | |||
| 2025-06-01 | 3dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵ | iximeow | |
| tweaks too | |||
| 2025-06-01 | expand isa feature selection to more bits | iximeow | |
| this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory | |||
| 2024-06-24 | rename most operand variants, make them structy rather than tupley | iximeow | |
| 2024-06-23 | add additional `call` test cases | iximeow | |
| fix 32-bit 66-prefixed ff /2 call not having 16-bit operands fix momentary regression in rendering `call` instructions to string | |||
| 2024-06-23 | InstructionTextBuffer is only present with alloc (new crate flag) | iximeow | |
| 2024-06-22 | NoColorsSink has a decent name now | iximeow | |
| 2024-06-22 | extract reusable display bits into yaxpeax-arch, add a visitor fn to Operand | iximeow | |
| comes with deleting the body of impl Colorize for Operand, because we can reuse the normal operand formatting code | |||
| 2024-06-21 | things compile again, add a few more caution signs around InstructionTextBuffer | iximeow | |
| 2024-06-20 | starting to get new DisplaySink stuff ready to extract... | iximeow | |
| 2024-06-19 | better testing for alternate sinks, fix hex formatting bug.... | iximeow | |
| 2024-06-18 | enough infratructure to avoid bounds checks, at incredible user cost | iximeow | |
| 2024-06-16 | commit unshippable wildly unsafe asm-filled printing code | iximeow | |
| write_2 will never actually be used, but im adapting it into contextualize in a... better way | |||
| 2024-04-02 | display opt: mem size labels and minor segment reporting changes | iximeow | |
| for mem size labels: add one new "BUG" entry at the start of the array so `mem_size` does not need to be adjusted before being used to look up a string from the `MEM_SIZE_STRINGS` array. it's hard to measure the direct benefit of this, but it shrinks codegen size by a bit and simplfies a bit of assembly.... for segment reporting changes: stos/scas/lods do not actually need special segment override logic. instead, set their use of `es` when decoded, if appropriate. this is potentially ambiguous; in non-64bit modes the sequence `26aa` would decode as `stos` with explicit `es` prefix. this is now identical to simply decoding `aa`, which now also reports that there is an explicit `es` prefix even though there is no prefix on tne instruction. on the other hand, the prefix-reported segment now more accurately describes the memory selector through which memory accesses will happen. seems ok? | |||
| 2023-12-16 | fix hreset being disassembled as having second operand of "Nothing" | iximeow | |
| just report it having one operand... | |||
| 2023-12-16 | fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` set | iximeow | |
| 2023-12-16 | fix incorrect register selection for `vpmov*2m` with `rex.r` set | iximeow | |
| 2023-12-16 | fix incorrect register selection for `vpmovm2*` with `rex.b` set | iximeow | |
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index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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