| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-04-19 | warnings, crc32 test | iximeow | |
| 2026-04-19 | a few more straggler instructions | iximeow | |
| 2026-04-19 | the rest of sse? | iximeow | |
| 2026-04-19 | substantially more sse coverage | iximeow | |
| 2026-04-17 | TODO: 32/16, maskmov{q,dqu} memory access size | iximeow | |
| 2026-04-17 | more precise about 0f0d prefetch/nop | iximeow | |
| 2026-04-12 | check and support more 0fXX opcodes | iximeow | |
| 2026-04-12 | sgdt/lidt/lgdt test fixes | iximeow | |
| 2026-04-12 | test table management instructions ({l,s}{g,i,l}dt) | iximeow | |
| these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know! | |||
| 2026-04-12 | many conditional instructions, jump, call, and start testing 0f opcodes | iximeow | |
| 2026-03-29 | rip out the kvm bits into a standalone crate | iximeow | |
| 2026-03-28 | full range | iximeow | |
| 2026-03-28 | last few weird cases unsuitable for generic testing | iximeow | |
| 2026-03-28 | handle instructions that read and write different parts of the same instruction | iximeow | |
| the motivating case is `xchg ah, al`, where both register writes independently "don't match" the overall register diff of the low 16 bits. the diff-checking code was too narrow: we really have to collect all allowed diffs on a register for an instruction and compare the actual diff to that unification. the implementation goes the other way though: compute the diff, and remove parts of the diff that are unaccounted for. if any diff remains, that is by definition unexpected and an error. | |||
| 2026-03-28 | more behavior, the rest of two-byte instructions? | iximeow | |
| 2026-03-27 | more accurate mov seg-to-gpr operand size | iximeow | |
| 2026-03-27 | test infra for segment regs, push/pop small regs | iximeow | |
| 2026-03-27 | push/pop for segment registers has implicit memory access | iximeow | |
| 2026-03-27 | div ops, mul ops, some other | iximeow | |
| 2026-03-19 | more instructions, figured out mul/imul | iximeow | |
| 2026-03-09 | back at it with more instruction behaviors and carveouts | iximeow | |
| 2026-03-09 | separate: more implicit operand size bits | iximeow | |
| 2026-03-09 | stop relying on mmio for behavior validation | iximeow | |
| first, the vcpu is configured with 1G pages, which confound linux's gva->gpa translation done as part of instruction emulation. this means that we get bogus faults in perfectly valid virtual addresses that the hardware can use, but linux cannot. second, relying on mmio means every mmio-trapped instruction is actually testing yaxpeax-x86 semantics against linux x86 emulation. while this is interesting, it is not the goal of the tests. maybe some later day! finally, write_matches_reg() had an inappropriate mask for what bits can be written given a certain register size. | |||
| 2026-03-02 | this might actually work omggggg | iximeow | |
| 2026-03-02 | cleanup, document, etc | iximeow | |
| 2026-03-02 | ok, gdt works... (mem16:32 means 32-bit offset THEN 16-bit selector???) | iximeow | |
| 2026-02-23 | set up an IDT, and try to use it, but just discover the GDT is actually broken | iximeow | |
| also shrink the GDT to 256 entries because i really won't use 8k of them. this makes the GDT entries only 0x400 bytes but i still skip a page from gdt_addr() to idt_addr(). | |||
| 2026-02-23 | more expansive access behavior validation, start on implicit op lists | iximeow | |
| 2026-02-23 | if tripped over a kvm bug i swear | iximeow | |
| 2026-02-23 | cleanup | iximeow | |
| 2026-02-23 | more reworking of vm and test harness | iximeow | |
| 2026-02-23 | lmao this rules | iximeow | |
| 2026-02-22 | correct push-immediate memory access sizeHEADno-gods-no- | iximeow | |
| 2025-09-29 | fix broken capstone_bench stuff, might delete later, idk | iximeow | |
| 2025-09-29 | annotation description test requires `fmt` | iximeow | |
| this was missed in typical testing because either tests run with all features, no features, or fmt. there wasn't a test entry for only std, which was broken. | |||
| 2025-06-01 | 3dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵ | iximeow | |
| tweaks too | |||
| 2025-06-01 | expand isa feature selection to more bits | iximeow | |
| this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory | |||
| 2024-06-24 | rename most operand variants, make them structy rather than tupley | iximeow | |
| 2024-06-23 | add additional `call` test cases | iximeow | |
| fix 32-bit 66-prefixed ff /2 call not having 16-bit operands fix momentary regression in rendering `call` instructions to string | |||
| 2024-06-23 | InstructionTextBuffer is only present with alloc (new crate flag) | iximeow | |
| 2024-06-22 | NoColorsSink has a decent name now | iximeow | |
| 2024-06-22 | extract reusable display bits into yaxpeax-arch, add a visitor fn to Operand | iximeow | |
| comes with deleting the body of impl Colorize for Operand, because we can reuse the normal operand formatting code | |||
| 2024-06-21 | things compile again, add a few more caution signs around InstructionTextBuffer | iximeow | |
| 2024-06-20 | starting to get new DisplaySink stuff ready to extract... | iximeow | |
| 2024-06-19 | better testing for alternate sinks, fix hex formatting bug.... | iximeow | |
| 2024-06-18 | enough infratructure to avoid bounds checks, at incredible user cost | iximeow | |
| 2024-06-16 | commit unshippable wildly unsafe asm-filled printing code | iximeow | |
| write_2 will never actually be used, but im adapting it into contextualize in a... better way | |||
| 2024-04-02 | display opt: mem size labels and minor segment reporting changes | iximeow | |
| for mem size labels: add one new "BUG" entry at the start of the array so `mem_size` does not need to be adjusted before being used to look up a string from the `MEM_SIZE_STRINGS` array. it's hard to measure the direct benefit of this, but it shrinks codegen size by a bit and simplfies a bit of assembly.... for segment reporting changes: stos/scas/lods do not actually need special segment override logic. instead, set their use of `es` when decoded, if appropriate. this is potentially ambiguous; in non-64bit modes the sequence `26aa` would decode as `stos` with explicit `es` prefix. this is now identical to simply decoding `aa`, which now also reports that there is an explicit `es` prefix even though there is no prefix on tne instruction. on the other hand, the prefix-reported segment now more accurately describes the memory selector through which memory accesses will happen. seems ok? | |||
| 2023-12-16 | fix hreset being disassembled as having second operand of "Nothing" | iximeow | |
| just report it having one operand... | |||
| 2023-12-16 | fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` set | iximeow | |
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index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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