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11 hours66-prefixed sha1rnds4 doesnt even realiximeow
12 hourspusha/popa/push-imm memory sizesiximeow
12 hoursworking through a bunch of avx512 stuff, regspec constructors are constiximeow
12 hourspextr*/extractpsiximeow
12 hoursinvept precisioniximeow
12 hoursmore precision for vinsert/vextract/vblendv{ps,pd}iximeow
12 hoursactually support avx/f16c in per-uarch decodingiximeow
12 hoursvmaskmovdqu, vmovq were also incorrect in some ways...iximeow
13 hoursmore general avx improvementsiximeow
13 hourscleanup pass on vex-encoded instructions is going to be excitingiximeow
13 hoursmaskmov{q,dqu} memory access sizeiximeow
13 hoursmore precise about 0f0d prefetch/nopiximeow
13 hoursfix table management instructions' ({l,s}{g,i,l}dt) mem_sizeiximeow
these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know!
13 hoursmore accurate mov seg-to-gpr operand sizeiximeow
13 hourspush/pop for segment registers has implicit memory accessiximeow
13 hourspushf, popf, enter, leave, xlat all have implicit memory accessiximeow
also add "is_masked" to operand spec
2026-02-22correct push-immediate memory access sizeiximeow
2025-09-29fix broken capstone_bench stuff, might delete later, idkiximeow
2025-09-29annotation description test requires `fmt`iximeow
this was missed in typical testing because either tests run with all features, no features, or fmt. there wasn't a test entry for only std, which was broken.
2025-06-013dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵iximeow
tweaks too
2025-06-01expand isa feature selection to more bitsiximeow
this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory
2024-06-24rename most operand variants, make them structy rather than tupleyiximeow
2024-06-23add additional `call` test casesiximeow
fix 32-bit 66-prefixed ff /2 call not having 16-bit operands fix momentary regression in rendering `call` instructions to string
2024-06-23InstructionTextBuffer is only present with alloc (new crate flag)iximeow
2024-06-22NoColorsSink has a decent name nowiximeow
2024-06-22extract reusable display bits into yaxpeax-arch, add a visitor fn to Operandiximeow
comes with deleting the body of impl Colorize for Operand, because we can reuse the normal operand formatting code
2024-06-21things compile again, add a few more caution signs around InstructionTextBufferiximeow
2024-06-20starting to get new DisplaySink stuff ready to extract...iximeow
2024-06-19better testing for alternate sinks, fix hex formatting bug....iximeow
2024-06-18enough infratructure to avoid bounds checks, at incredible user costiximeow
2024-06-16commit unshippable wildly unsafe asm-filled printing codeiximeow
write_2 will never actually be used, but im adapting it into contextualize in a... better way
2024-04-02display opt: mem size labels and minor segment reporting changesiximeow
for mem size labels: add one new "BUG" entry at the start of the array so `mem_size` does not need to be adjusted before being used to look up a string from the `MEM_SIZE_STRINGS` array. it's hard to measure the direct benefit of this, but it shrinks codegen size by a bit and simplfies a bit of assembly.... for segment reporting changes: stos/scas/lods do not actually need special segment override logic. instead, set their use of `es` when decoded, if appropriate. this is potentially ambiguous; in non-64bit modes the sequence `26aa` would decode as `stos` with explicit `es` prefix. this is now identical to simply decoding `aa`, which now also reports that there is an explicit `es` prefix even though there is no prefix on tne instruction. on the other hand, the prefix-reported segment now more accurately describes the memory selector through which memory accesses will happen. seems ok?
2023-12-16fix hreset being disassembled as having second operand of "Nothing"iximeow
just report it having one operand...
2023-12-16fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` setiximeow
2023-12-16fix incorrect register selection for `vpmov*2m` with `rex.r` setiximeow
2023-12-16fix incorrect register selection for `vpmovm2*` with `rex.b` setiximeow
2023-12-16abnormal memory sizes for keylocker instructions are not bugsiximeow
new `does_not_decode_invalid_registers` fuzzer found other bugs! the 384-bit accesses for 128b keylocker instructions are an otherwise-unknown size and had a memory size of `BUG`. they are not bugs. give the memory size a real name.
2023-12-16fix opportunity for unhandled register synonymsiximeow
registers `al`, `cl`, `dl`, and `bl` could have two different representations - with `rex.w` and without. these two forms of `RegSpec` would not compare equal, nor has the same, so for code relying on `RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these synonyms would introduce bugs in register analysis. for example, in `yaxpeax-core`, this would result in instructions writing to `rex.w al` not being visible as definitions for a future read of `!rex.w al`. fix this in `x86_64` code, add new test cases about the confusion, adjust register names to make this situation more clearly a bug, and introduce two new fuzz targets that would have helped spot this error.
2023-12-15more RegSpec constructor validation, fix bug in x86_64 1b reg specsiximeow
* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9
2023-07-24fix handling of lar/lsl source registeriximeow
2023-07-23fix inconsistently-poreted memory access size of vcvt{,t}{sd,si}iximeow
2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-16forward changes along to 16-bit decoder...iximeow
2023-07-16forward changes along to 32-bit decoder...iximeow
2023-07-08annotation ordering changed a bit in refactoring, for the better???iximeow
2023-07-08fix v(p)gather situations, get vex tests passing againiximeow
2023-07-05fix operand handling for the psl/psr family of xmm shifts/rotatesiximeow
these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed)
2023-07-04two more test casesiximeow
2023-07-04fix some dancing between bank size and RegisterBank enum valuesiximeow
in the process, fixed a decoding bug dealing with a0/a1/a2/a3 movs (respected rex.b when rex.b should have been ignored) this seems to maybe improve runtime ever so slightly, but this is really meant as a cleanup commit more than anything.
2023-03-05add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpersiximeow
this request/suggestion comes from [github](https://github.com/iximeow/yaxpeax-x86/issues/29)! thank you!
generated by cgit v1.1 at 2026-05-25 13:31:40 +0000