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2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present
2020-05-03add width() to ask width of an x86 operandiximeow
this is largely wrong for memory operands, which require more invasive changes
2020-05-03that instruction is cwd, not cbdiximeow
2020-05-03bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffiiximeow
2020-03-22yaxpeax-x86 decodes in 32-bit mode nowiximeow
2020-02-22remove unused functioniximeow
2020-02-22support most avx operand codesiximeow
avx is still incomplete, but less so avx is still practically untested
2020-02-22fix {jmp,call} <reg>, as well as jmpf/callfiximeow
also support vmxon to finish out the f30f opcode map add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't provide a way to distinguish different operand sizes (yet)
2020-02-22more sse/sse2 supportiximeow
largely f20f/f30f opcode map items
2020-02-22add vmclear testiximeow
this instruction is decoded with the sse2 660f map but not actually added in sse2
2020-02-22support 660f sse2 instructionsiximeow
this isn't quite all of sse2, but gets close. the f20f opcode map still needs some touching up. also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand
2020-02-16embarassingly had OperandSpec variants for modrm displacement == 0 backwardsiximeow
2020-02-11support `in` and `out` instructionsiximeow
2020-02-11add `RegSpec::name` to get `&'static str` labels for registersiximeow
2020-01-15support "int imm8" instructionsiximeow
2020-01-15make space for non-64bit modesiximeow
2020-01-15add more sse2 instructions (packed shift by immediate, mostly)iximeow
really need to adjust OperandCode, almost out of one-off options...
2020-01-15add 660f6* series instructions as well as 660f70iximeow
this adds in some missing sse2 instructions in the alternate secondary opcode map. because these were missing, instructions were incorrectly decoded from the 0f opcode map, yielding mmx-operand versions of themselves (usually) there are undoubtedly more missing sse2 instructions from the 660f map.
2020-01-15negative displacements were printed wrong, test against that for the futureiximeow
this was accidentally fixed in no_std-ing, the prior commit
2020-01-13explicitly fail to handle WAIT prefixiximeow
2020-01-13test that instruction lengths are correctiximeow
fix several instances of incorrect instruction lengths * immediates for `mov reg, imm` and some other instructions were double-counted * lengths for vex prefixes were wrong all over the place
2020-01-13add Default impl for Instruction to track yaxpeax-archiximeow
2020-01-12"fix warnings"iximeow
this assists many misdecodes from being totally wrong to only slightly wrong and more clear about it (rrr-selected opcodes or W-bit-selected opcodes were accidentally decoded as the first variant of their opcode) also fixes sillier warnings all over the place, and probably a few incorrectly counted lengths
2020-01-12match changes in arch to have Resulty decode, instead of Optioniximeow
2020-01-12avx feature flag and avx/aesni instructions flagged properlyiximeow
2020-01-12support aesniiximeow
this includes respecting ModRM_XXXX-style operand codes from alternate 0f opcode maps. this MAY introduce bugs where an opcode 0fXX is valid by the 0f map, invalid by the 660f map, and we see a sequence like 660fXXYY. if YY results in 0fXX being invalid by 660f, we may have to fall back to reading opcode XX as an 0f opcode, where YY needs to be re-read with the correct operand code. hopefully this doesn't actually happen...
2020-01-12support missing sse3 instructions, add tests for sse3 instructionsiximeow
2020-01-12test fence instructions against different quirks modesiximeow
add enclv instruction add sse3, ssse3, sse4.1, and sse4.2 feature flags, plus a host of missing opcodes
2020-01-12add a slew of system-y instructions, as well as cpu quirks for amd/intel ↵iximeow
fence instructions
2020-01-12vex tests work!iximeow
2020-01-12vexiximeow
2020-01-12proper movs operand supportiximeow
2020-01-12pshuf/psr/shld/shrd plus some test fixesiximeow
this makes all current non-vex/evex tests pass!!!
2020-01-12down to one failing test, for nowiximeow
2020-01-12more cvt variantsiximeow
2020-01-12improved cvts again, movd/movqiximeow
2020-01-12add pxor and some others, support mm operandsiximeow
2020-01-12support ucomiss, cvt*, some other sse instructionsiximeow
2020-01-12more careful prefix handlingiximeow
2020-01-12support prefetch, movlps, movhps, refine prefix permissivityiximeow
rep, repz, repnz prefixes are only displayed on instructions for which they have a semantic effect. movs, cmps, scas, lods, stos, ins, and outs are now decodable.
2020-01-12fix 0x98 and 0x99 opcodes, lss/lfs/lgs decodesiximeow
also remove unnecessary variants in unlikely_operands and adjust expectations of several tests
2020-01-12add display rules for new opcodes, continuing to fix testsiximeow
2020-01-12properly handle excessive prefixes on 0f-category instructioniximeow
also initial support for 660f opcode map, though it's all invalid instructions fix backwards base and index registers for memory operands with both fix incorrect test
2020-01-12hack to handle prefixed sequences that might appear to be escaped opcodesiximeow
2020-01-12support imul, >2 operands, and 4-bit register bankiximeow
2020-01-12most non-avx (really, non-vex) instructionsiximeow
2020-01-12that println shouldnt be benchmarkediximeow
2020-01-12update lar testsiximeow
2020-01-12display impl doesnt show memory operand sizesiximeow
2020-01-12decode shift-by-cl and fix error decoding sign-extending operandsiximeow
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