warnings-b-gone

2 files changed, 32 insertions, 25 deletions

diff --git a/src/armv7.rs b/src/armv7.rs
index 03d4b77..9fe6fea 100644
--- a/src/armv7.rs
+++ b/src/armv7.rs
@@ -1,5 +1,5 @@
-#[cfg(feature="use-serde")]
-use serde::{Serialize, Deserialize};
+//#[cfg(feature="use-serde")]
+//use serde::{Serialize, Deserialize};
 
 use std::fmt::{Display, Formatter};
 
@@ -15,7 +15,7 @@ impl Display for ConditionedOpcode {
 
 #[allow(non_snake_case)]
 impl <T: std::fmt::Write> ShowContextual<u32, [Option<String>], T> for Instruction {
-    fn contextualize(&self, colors: Option<&ColorSettings>, address: u32, context: Option<&[Option<String>]>, out: &mut T) -> std::fmt::Result {
+    fn contextualize(&self, colors: Option<&ColorSettings>, _address: u32, _context: Option<&[Option<String>]>, out: &mut T) -> std::fmt::Result {
         match self.opcode {
             Opcode::LDR(true, false, false) => {
                 match self.operands {
@@ -94,8 +94,9 @@ impl <T: std::fmt::Write> ShowContextual<u32, [Option<String>], T> for Instructi
                     _ => { unreachable!(); }
                 }
             }
-            Opcode::STM(add, pre, wback, usermode) |
-            Opcode::LDM(add, pre, wback, usermode) => {
+            // TODO: [add, pre, usermode]
+            Opcode::STM(_add, _pre, wback, _usermode) |
+            Opcode::LDM(_add, _pre, wback, _usermode) => {
                 match self.operands {
                     Operands::RegRegList(Rr, list) => {
                         ConditionedOpcode(self.opcode, self.condition).colorize(colors, out)?;
@@ -132,13 +133,15 @@ impl <T: std::fmt::Write> ShowContextual<u32, [Option<String>], T> for Instructi
                         write!(out, " {}, ", reg_name_colorize(r, colors))?;
                         format_reg_list(out, list, colors)?;
                     },
-                    Operands::TwoRegImm(a, b, imm) => {
+                    Operands::TwoRegImm(_a, _b, _imm) => {
+                        // TODO:
                         write!(out, " <unimplemented>")?;
                     },
                     Operands::ThreeOperand(a, b, c) => {
                         write!(out, " {}, {}, {}", reg_name_colorize(a, colors), reg_name_colorize(b, colors), reg_name_colorize(c, colors))?;
                     },
-                    Operands::ThreeOperandImm(a, b, imm) => {
+                    Operands::ThreeOperandImm(_a, _b, _imm) => {
+                        // TODO:
                         write!(out, " <unimplemented>")?;
                     },
                     Operands::ThreeOperandWithShift(a, b, c, shift) => {
@@ -148,7 +151,8 @@ impl <T: std::fmt::Write> ShowContextual<u32, [Option<String>], T> for Instructi
                     Operands::MulThreeRegs(a, b, c) => {
                         write!(out, " {}, {}, {}", reg_name_colorize(a, colors), reg_name_colorize(b, colors), reg_name_colorize(c, colors))?;
                     },
-                    Operands::MulFourRegs(a, b, c, d) => {
+                    Operands::MulFourRegs(_a, _b, _c, _d) => {
+                        // TODO:
                         write!(out, " <unimplemented>")?;
                     },
                     Operands::BranchOffset(imm) => {
@@ -655,7 +659,7 @@ impl ConditionCode {
             0b1100 => ConditionCode::GT,
             0b1101 => ConditionCode::LE,
             0b1110 => ConditionCode::AL,
-            _ => unsafe {
+            _ => {
                 // this means the argument `value` must never be outside [0,15]
                 // which itself means this function shouldn't be public
                 unreachable!();
@@ -897,7 +901,7 @@ impl Decodable for Instruction {
                     // |c o n d|0 0 0 x|x x x x x x x x x x x x x x x x|1 0 1 1|x x x x|
                     // page A5-201
                                 self.opcode = Opcode::Incomplete(word);
-                                return Some(());
+                                // return Some(());
                                 match flags {
                                     0b00010 => {
                                         // self.opcode = Opcode::STRHT_sub;
@@ -925,6 +929,7 @@ impl Decodable for Instruction {
                                         unreachable!();
                                     }
                                 }
+                                panic!("page a5-201");
                             }
                             0b10 => {
                     // |c o n d|0 0 0 x|x x x x x x x x x x x x x x x x|1 1 0 1|x x x x|
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index e58d2a2..3e0403a 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -1,9 +1,9 @@
-#[cfg(feature="use-serde")]
-use serde::{Serialize, Deserialize};
+//#[cfg(feature="use-serde")]
+//use serde::{Serialize, Deserialize};
 
 use std::fmt::{Display, Formatter};
 
-use yaxpeax_arch::{Arch, Colorize, Colored, ColorSettings, Decodable, LengthedInstruction, ShowContextual, YaxColors};
+use yaxpeax_arch::{Arch, ColorSettings, Decodable, LengthedInstruction, ShowContextual};
 
 #[allow(non_snake_case)]
 mod docs {
@@ -118,7 +118,7 @@ mod docs {
 
 #[allow(non_snake_case)]
 impl <T: std::fmt::Write> ShowContextual<u64, [Option<String>], T> for Instruction {
-    fn contextualize(&self, colors: Option<&ColorSettings>, address: u64, context: Option<&[Option<String>]>, out: &mut T) -> std::fmt::Result {
+    fn contextualize(&self, _colors: Option<&ColorSettings>, _address: u64, _context: Option<&[Option<String>]>, out: &mut T) -> std::fmt::Result {
         write!(out, "{}", self)
     }
 }
@@ -1545,7 +1545,7 @@ impl Decodable for Instruction {
                         } else {
                             self.opcode = Opcode::Invalid;
                         }
-                        unreachable!();
+                        unreachable!("decode Rd: {}, Rn: {}, imms: {}, Rm: {}, No0: {}", Rd, Rn, imms, Rm, No0);
                     }
                     _ => { unreachable!() }
                 }
@@ -1605,7 +1605,8 @@ impl Decodable for Instruction {
                             _ => {
                                 Opcode::Invalid
                             }
-                        }
+                        };
+                        unreachable!("Rt: {}, Rn: {}, Rt2: {}, Rs: {}", Rt, Rn, Rt2, Rs);
                     },
                     0b00001 => {
                         let Rt = (word & 0x1f) as u16;
@@ -1643,6 +1644,7 @@ impl Decodable for Instruction {
                             Operand::Nothing,
                             Operand::Nothing,
                         ];
+                        unreachable!("Rt: {}, Rn: {}, Rt2: {}, Rs: {}", Rt, Rn, Rt2, Rs);
                     },
                     0b01000 |
                     0b01001 => {
@@ -1687,19 +1689,19 @@ impl Decodable for Instruction {
                         let opc = (word >> 29) & 0x3;
                         let Rt = word & 0x1f;
                         let imm19 = (word >> 5) & 0x7fff;
-                        panic!("C3.3.5 V==1");
+                        panic!("C3.3.5 V==1. opc: {}, Rt: {}, imm19: {}", opc, Rt, imm19);
                     },
                     0b10000 => {
                         // load/store no-allocate pair (offset)
                         // V == 0
                         let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6);
-                        panic!("C3.3.7 V==0");
+                        panic!("C3.3.7 V==0, opc_L: {}", opc_L);
                     },
                     0b10100 => {
                         // load/store no-allocate pair (offset)
                         // V == 1
                         let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6);
-                        panic!("C3.3.7 V==1");
+                        panic!("C3.3.7 V==1, opc_L: {}", opc_L);
                     },
                     0b10001 => {
                         // load/store register pair (post-indexed)
@@ -1707,7 +1709,7 @@ impl Decodable for Instruction {
                         let Rt = (word & 0x1f) as u16;
                         let Rn = ((word >> 5) & 0x1f) as u16;
                         let Rt2 = ((word >> 10) & 0x1f) as u16;
-                        let mut imm7 = (((((word >> 15) & 0x7f) as i16) << 9) >> 9);
+                        let mut imm7 = ((((word >> 15) & 0x7f) as i16) << 9) >> 9;
                         let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6);
                         let size = match opc_L {
                             0b000 => {
@@ -1757,7 +1759,7 @@ impl Decodable for Instruction {
                         // load/store register pair (post-indexed)
                         // V == 1
                         let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6);
-                        panic!("C3.3.15 V==1");
+                        panic!("C3.3.15 V==1, opc_L: {}", opc_L);
                     },
                     0b10010 => {
                         // load/store register pair (offset)
@@ -1765,7 +1767,7 @@ impl Decodable for Instruction {
                         let Rt = (word & 0x1f) as u16;
                         let Rn = ((word >> 5) & 0x1f) as u16;
                         let Rt2 = ((word >> 10) & 0x1f) as u16;
-                        let mut imm7 = (((((word >> 15) & 0x7f) as i16) << 9) >> 9);
+                        let mut imm7 = ((((word >> 15) & 0x7f) as i16) << 9) >> 9;
                         let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6);
                         let size = match opc_L {
                             0b000 => {
@@ -1815,7 +1817,7 @@ impl Decodable for Instruction {
                         // load/store register pair (offset)
                         // V == 1
                         let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6);
-                        panic!("C3.3.14 V==1");
+                        panic!("C3.3.14 V==1, opc_L: {}", opc_L);
                     },
                     0b10011 => {
                         // load/store register pair (pre-indexed)
@@ -1823,7 +1825,7 @@ impl Decodable for Instruction {
                         let Rt = (word & 0x1f) as u16;
                         let Rn = ((word >> 5) & 0x1f) as u16;
                         let Rt2 = ((word >> 10) & 0x1f) as u16;
-                        let mut imm7 = (((((word >> 15) & 0x7f) as i16) << 9) >> 9);
+                        let mut imm7 = ((((word >> 15) & 0x7f) as i16) << 9) >> 9;
                         let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6);
                         let size = match opc_L {
                             0b000 => {
@@ -1873,7 +1875,7 @@ impl Decodable for Instruction {
                         // load/store register pair (pre-indexed)
                         // V == 1
                         let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6);
-                        panic!("C3.3.16 V==1");
+                        panic!("C3.3.16 V==1, opc_L: {}", opc_L);
                     },
                     0b11000 |
                     0b11001 => {