capstone/yax differences, test pac more comprehensively

2 files changed, 23 insertions, 30 deletions

diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index 5ea7f8e..0ca7bff 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -581,30 +581,17 @@ impl Display for Instruction {
             Opcode::HINT => {
                 if let (Operand::ControlReg(CRn), Operand::Immediate(op2)) = (self.operands[0], self.operands[1]) {
                     let hint_num = (CRn << 3) | op2 as u16;
-                    return match hint_num {
+                    return match hint_num & 0b111111 {
                         0 => { write!(fmt, "nop") },
                         1 => { write!(fmt, "yield") },
                         2 => { write!(fmt, "wfe") },
                         3 => { write!(fmt, "wfi") },
                         4 => { write!(fmt, "sev") },
-                        5 => { write!(fmt, "sevl") },
-                        7 => { write!(fmt, "xpaclri") },
-                        8 => { write!(fmt, "pacia1716") },
-                        10 => { write!(fmt, "pacib1716") },
-                        12 => { write!(fmt, "autia1716") },
-                        14 => { write!(fmt, "autib1716") },
-                        16 => { write!(fmt, "esb") },
-                        17 => { write!(fmt, "psb csync") },
-                        18 => { write!(fmt, "tsb csync") },
-                        20 => { write!(fmt, "csdb") },
-                        24 => { write!(fmt, "paciaz") },
-                        25 => { write!(fmt, "paciasp") },
-                        26 => { write!(fmt, "pacibz") },
-                        27 => { write!(fmt, "pacibsp") },
-                        28 => { write!(fmt, "autiaz") },
-                        29 => { write!(fmt, "autiasp") },
-                        30 => { write!(fmt, "autibz") },
-                        31 => { write!(fmt, "autibsp") },
+                        0x10 => { write!(fmt, "esb") },
+                        0x11 => { write!(fmt, "psb csync") },
+                        0x12 => { write!(fmt, "tsb csync") },
+                        0x14 => { write!(fmt, "csdb") },
+                        0x15 => { write!(fmt, "sevl") },
                         _ => { write!(fmt, "hint #{:#x}", hint_num) }
                     }
                 }
@@ -2931,9 +2918,11 @@ impl Display for Operand {
                 }
             }
             Operand::RegRegOffset(reg, index_reg, index_size, extend, amount) => {
-                if ((extend == &ShiftStyle::UXTW && index_size == &SizeCode::W) ||
-                   (extend == &ShiftStyle::UXTX && index_size == &SizeCode::X)) &&
-                    *amount == 0 {
+                if extend == &ShiftStyle::LSL && *amount == 0 {
+                    write!(fmt, "[{}, {}]", Operand::RegisterOrSP(SizeCode::X, *reg), Operand::Register(*index_size, *index_reg))
+                } else if ((extend == &ShiftStyle::UXTW && index_size == &SizeCode::W) ||
+                           (extend == &ShiftStyle::UXTX && index_size == &SizeCode::X)) &&
+                           *amount == 0 {
                     write!(fmt, "[{}, {}, {}]", Operand::RegisterOrSP(SizeCode::X, *reg), Operand::Register(*index_size, *index_reg), extend)
                 } else {
                     write!(fmt, "[{}, {}, {} #{}]", Operand::RegisterOrSP(SizeCode::X, *reg), Operand::Register(*index_size, *index_reg), extend, amount)
@@ -10314,7 +10303,7 @@ impl Decoder<ARMv8> for InstDecoder {
                                         Operand::Nothing,
                                         Operand::Nothing
                                     ];
-                                } else if (word & 0x1fffff) == 0x1f081f {
+                                } else if (word & 0x1ffc1f) == 0x1f081f {
                                     inst.opcode = Opcode::BRAAZ;
                                     inst.operands = [
                                         Operand::Register(SizeCode::X, Rn as u16),
@@ -10322,7 +10311,7 @@ impl Decoder<ARMv8> for InstDecoder {
                                         Operand::Nothing,
                                         Operand::Nothing,
                                     ];
-                                } else if (word & 0x1fffff) == 0x1f0c1f {
+                                } else if (word & 0x1ffc1f) == 0x1f0c1f {
                                     inst.opcode = Opcode::BRABZ;
                                     inst.operands = [
                                         Operand::Register(SizeCode::X, Rn as u16),
@@ -10345,7 +10334,7 @@ impl Decoder<ARMv8> for InstDecoder {
                                         Operand::Nothing,
                                         Operand::Nothing
                                     ];
-                                } else if (word & 0x1fffff) == 0x1f081f {
+                                } else if (word & 0x1ffc1f) == 0x1f081f {
                                     inst.opcode = Opcode::BLRAAZ;
                                     inst.operands = [
                                         Operand::Register(SizeCode::X, Rn as u16),
@@ -10353,7 +10342,7 @@ impl Decoder<ARMv8> for InstDecoder {
                                         Operand::Nothing,
                                         Operand::Nothing,
                                     ];
-                                } else if (word & 0x1fffff) == 0x1f0c1f {
+                                } else if (word & 0x1ffc1f) == 0x1f0c1f {
                                     inst.opcode = Opcode::BLRABZ;
                                     inst.operands = [
                                         Operand::Register(SizeCode::X, Rn as u16),
@@ -10456,7 +10445,7 @@ impl Decoder<ARMv8> for InstDecoder {
                             }
                         } else if opc == 0b001 {
                             // implied leading bit means opc = 0b1001
-                            if word & 0xff_ff_fc_00 == 0xd7_1f_0c_00 {
+                            if word & 0xff_ff_fc_00 == 0xd7_3f_08_00 {
                                 // op3 = 000011
                                 // register modifier variant
                                 inst.opcode = Opcode::BLRAA;
@@ -10467,7 +10456,7 @@ impl Decoder<ARMv8> for InstDecoder {
                                     Operand::Nothing,
                                     Operand::Nothing,
                                 ];
-                            } else if word & 0xff_ff_fc_00 == 0xd7_1f_08_00 {
+                            } else if word & 0xff_ff_fc_00 == 0xd7_3f_0c_00 {
                                 // op3 = 000011
                                 inst.opcode = Opcode::BLRAB;
 
diff --git a/test/armv8/a64.rs b/test/armv8/a64.rs
index 8d34a04..1dea7e1 100644
--- a/test/armv8/a64.rs
+++ b/test/armv8/a64.rs
@@ -4183,8 +4183,8 @@ fn test_openblas_misc_ops() {
         ([0x54, 0xd0, 0x3b, 0xd5], "mrs x20, tpidr_el0"),
         ([0x41, 0xe0, 0x3b, 0xd5], "mrs x1, cntvct_el0"),
         ([0x55, 0xe0, 0x3b, 0xd5], "mrs x21, cntvct_el0"),
-        ([0xe2, 0x69, 0xb6, 0xf8], "prfm pldl2keep, [x15, x22, lsl #0]"),
-        ([0x00, 0x6a, 0xb7, 0xf8], "prfm pldl1keep, [x16, x23, lsl #0]"),
+        ([0xe2, 0x69, 0xb6, 0xf8], "prfm pldl2keep, [x15, x22]"),
+        ([0x00, 0x6a, 0xb7, 0xf8], "prfm pldl1keep, [x16, x23]"),
         ([0x80, 0x00, 0x80, 0xf9], "prfm pldl1keep, [x4]"),
         ([0x81, 0x00, 0x80, 0xf9], "prfm pldl1strm, [x4]"),
         ([0x00, 0x02, 0x80, 0xf9], "prfm pldl1keep, [x16]"),
@@ -4772,7 +4772,9 @@ fn test_uq() {
 fn test_cfi() {
     const TESTS: &[([u8; 4], &'static str)] = &[
         ([0x1f, 0x08, 0x1f, 0xd6], "braaz x0"),
+        ([0x3f, 0x08, 0x1f, 0xd6], "braaz x1"),
         ([0x00, 0x08, 0x1f, 0xd7], "braa x0, x0"),
+        ([0x00, 0x08, 0x3f, 0xd7], "blraa x0, x0"),
     ];
     let errs = run_tests(TESTS);
 
@@ -4864,6 +4866,8 @@ fn test_misc() {
         ([0x00, 0x30, 0xc0, 0x9a], "pacga x0, x0, x0"),
         ([0x00, 0x00, 0xae, 0x9e], "fmov x0, v0.d[1]"),
         ([0x00, 0x00, 0xe6, 0x9e], "fmov x0, h0"),
+        ([0x7f, 0x41, 0x00, 0xd5], "msr pstate.58, #0x1"),
+        ([0x00, 0x68, 0x20, 0x38], "strb w0, [x0, x0]"),
     ];
     let errs = run_tests(TESTS);