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| author | iximeow <me@iximeow.net> | 2021-12-27 20:35:18 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-12-27 20:35:18 -0800 |
| commit | b1d0fc26e1c4757953ef80c92c7a4e82c0d698cf (patch) | |
| tree | c3830f163375de520dc24e1ccaf0c5d46c8c1561 | |
| parent | f2b625ebdb0f8a17644eeda1d3fad182bf3cfb99 (diff) | |
confused scalar and non-scalar simd tables
| -rw-r--r-- | src/armv8/a64.rs | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index 3aaa7ef..a38511d 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -5107,11 +5107,7 @@ impl Decoder<ARMv8> for InstDecoder { Err(DecodeError::InvalidOperand), Ok((Q, D, Q, D)), ]; - if opcode == 0b00011 { - // AND, BIC, ORR, ORN - // EOR, BSL, BIT, BIF - return Err(DecodeError::IncompleteDecoder); - } else if opcode < 0b11000 { + if opcode < 0b11000 { // TODO: validate operands const OPCODES_U0_LOW: &[Result<(Opcode, &'static OperandSizeTable), DecodeError>] = &[ Err(DecodeError::InvalidOpcode), |