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| author | iximeow <me@iximeow.net> | 2021-12-29 01:58:27 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-12-29 01:58:27 -0800 |
| commit | 611a375a524fcdee098ae7fae00c5498ff0d1465 (patch) | |
| tree | b4e71d2d267797a946382151b6de4a79b47a61c9 | |
| parent | 9967fba9f8f8449626692e336ff4d44823f036fc (diff) | |
stxrb memory operand error
| -rw-r--r-- | src/armv8/a64.rs | 4 | ||||
| -rw-r--r-- | test/armv8/a64.rs | 14 |
2 files changed, 16 insertions, 2 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index 9d94c1a..8b96f60 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -6844,14 +6844,14 @@ impl Decoder<ARMv8> for InstDecoder { inst.operands = [ Operand::Register(SizeCode::W, Rs), Operand::Register(SizeCode::W, Rt), - Operand::RegisterOrSP(SizeCode::X, Rn), + Operand::RegOffset(Rn, 0), Operand::Nothing, ]; } else if Lo1 == 0b10 { // load ops inst.operands = [ Operand::Register(SizeCode::W, Rt), - Operand::RegisterOrSP(SizeCode::X, Rn), + Operand::RegOffset(Rn, 0), Operand::Nothing, Operand::Nothing, ]; diff --git a/test/armv8/a64.rs b/test/armv8/a64.rs index be1f486..c7bddf7 100644 --- a/test/armv8/a64.rs +++ b/test/armv8/a64.rs @@ -4355,6 +4355,20 @@ fn test_weird_str() { } #[test] +fn test_mismatches() { + const TESTS: &[([u8; 4], &'static str)] = &[ + ([0x00, 0x00, 0x00, 0x08], "stxrb w0, w0, [x0]"), + ]; + let errs = run_tests(TESTS); + + for err in errs.iter() { + println!("{}", err); + } + + assert!(errs.is_empty()); +} + +#[test] fn test_cas() { const TESTS: &[([u8; 4], &'static str)] = &[ ([0x20, 0x7c, 0x20, 0x08], "casp w0, w1, w0, w1, [x1]"), |