fix missing decode of `s` bit for wide shift/rotate ops

3 files changed, 19 insertions, 0 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 835d41b..30b3866 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -15,6 +15,7 @@
 * thumb2: `mrs` destinations, which should have been a mask of the current (or
   saved) program status register, was reported as a banked GPR.
 * thumb2: some coprocessor instructions were incorrectly decoded as `ldc*/stc*`
+* thumb2: fix missing decode of `s` bit for wide lsl/lsr/asr/ror (register)
 * ARMv8: support thumb2 encoding of `Test Target` instruction, `Opcode::TT`
   (formatted as any of `tt`, `ttt`, `tta`, `ttat`)
 * ARMv8: formerly-coprocessor instructions have been defined into SIMD extensions,
diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs
index 45c8917..18b4526 100644
--- a/src/armv7/thumb.rs
+++ b/src/armv7/thumb.rs
@@ -2762,6 +2762,7 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d
                             if !op2[3] {
                                 // `LSL`, `LSR`, `ASR`, `ROR`
                                 // v6T2
+                                inst.set_s(instr2[4]);
                                 let op = [
                                     Opcode::LSL,
                                     Opcode::LSR,
diff --git a/tests/armv7/thumb.rs b/tests/armv7/thumb.rs
index 43d7638..defdacb 100644
--- a/tests/armv7/thumb.rs
+++ b/tests/armv7/thumb.rs
@@ -3194,6 +3194,23 @@ fn test_decode_op_s_cases() {
         &[0xff, 0x37],
         "adds r7, 0xff"
     );
+
+    test_display(
+        &[0x7c, 0xfa, 0xe, 0xfe],
+        "rors.w lr, ip, lr"
+    );
+    test_display(
+        &[0x5b, 0xfa, 0xe, 0xfe],
+        "asrs.w lr, fp, lr"
+    );
+    test_display(
+        &[0x32, 0xfa, 0xe, 0xfe],
+        "lsrs.w lr, r2, lr"
+    );
+    test_display(
+        &[0x16, 0xfa, 0xe, 0xfe],
+        "lsls.w lr, r6, lr"
+    );
 }
 #[test]
 fn test_decode_pop_cases() {