diff options
| author | iximeow <me@iximeow.net> | 2020-12-06 15:37:46 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2020-12-06 15:37:46 -0800 |
| commit | 44542e4f40f13dbdc10ec491b50178bb39fc6ca1 (patch) | |
| tree | 246bf6080677847374b25ac2d3d90ef9404bdd36 /src/armv7.rs | |
| parent | 1572e928b41b5c0765d7f47b346110da14e58b9e (diff) | |
support CPS (change processor state) and some warming cleanup
Diffstat (limited to 'src/armv7.rs')
| -rw-r--r-- | src/armv7.rs | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/armv7.rs b/src/armv7.rs index d98cfb0..bd4629e 100644 --- a/src/armv7.rs +++ b/src/armv7.rs @@ -94,14 +94,18 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> ShowContextual<u3 } Opcode::CPS(_) => { if let Operand::Imm12(aif) = &self.operands[0] { - return write!( + write!( out, "{} {}{}{}", &self.opcode, if aif & 0b100 != 0 { "a" } else { "" }, if aif & 0b010 != 0 { "i" } else { "" }, if aif & 0b001 != 0 { "f" } else { "" }, - ); + )?; + if let Operand::Imm12(mode) = &self.operands[1] { + write!(out, ", #{:x}", mode)?; + } + return Ok(()); } else { panic!("impossible cps operand"); } @@ -136,7 +140,7 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> ShowContextual<u3 Opcode::LDM(true, false, false, _usermode) => { // TODO: what indicates usermode in the ARM syntax? match self.operands { - [Operand::RegWBack(Reg { bits: 13 }, wback), Operand::RegList(list), Operand::Nothing, Operand::Nothing] => { + [Operand::RegWBack(Reg { bits: 13 }, true), Operand::RegList(list), Operand::Nothing, Operand::Nothing] => { ConditionedOpcode(Opcode::POP, self.s(), self.w(), self.condition).colorize(colors, out)?; write!(out, " ")?; return format_reg_list(out, list, colors); @@ -147,7 +151,7 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> ShowContextual<u3 Opcode::STM(false, true, false, _usermode) => { // TODO: what indicates usermode in the ARM syntax? match self.operands { - [Operand::RegWBack(Reg { bits: 13 }, wback), Operand::RegList(list), Operand::Nothing, Operand::Nothing] => { + [Operand::RegWBack(Reg { bits: 13 }, true), Operand::RegList(list), Operand::Nothing, Operand::Nothing] => { ConditionedOpcode(Opcode::PUSH, self.s(), self.w(), self.condition).colorize(colors, out)?; write!(out, " ")?; return format_reg_list(out, list, colors); @@ -575,6 +579,7 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> Colorize<T, Color Opcode::DBG | Opcode::CPS(_) | + Opcode::CPS_modeonly | Opcode::SETEND | Opcode::ENTERX | Opcode::LEAVEX | @@ -782,6 +787,7 @@ impl Display for Opcode { Opcode::CBNZ => { write!(f, "cbnz") }, Opcode::SETEND => { write!(f, "setend") }, Opcode::CPS(disable) => { write!(f, "cps{}", if *disable { "id" } else { "ie" }) }, + Opcode::CPS_modeonly => { write!(f, "cps") }, Opcode::REV => { write!(f, "rev") }, Opcode::REV16 => { write!(f, "rev16") }, Opcode::REVSH => { write!(f, "revsh") }, @@ -987,6 +993,7 @@ pub enum Opcode { CBNZ, SETEND, CPS(bool), + CPS_modeonly, REV, REV16, REVSH, |