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authoriximeow <me@iximeow.net>2026-07-26 17:56:26 +0000
committeriximeow <me@iximeow.net>2026-07-28 07:28:15 +0000
commit9b3c56c0e62c3d1c27ffef4b8021663798b73ca7 (patch)
tree212b04bd20e3a1b1ec1e9e2296986389b70ef31d /src/armv7/display.rs
parent019920be5aa0b3b129a4ecf3bc31c14fddf34eff (diff)
thumb: when nonconforming, allow it/cond=1111 like capstone
Diffstat (limited to 'src/armv7/display.rs')
-rw-r--r--src/armv7/display.rs11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/armv7/display.rs b/src/armv7/display.rs
index 6f6fba1..d2198de 100644
--- a/src/armv7/display.rs
+++ b/src/armv7/display.rs
@@ -620,8 +620,15 @@ pub(crate) fn visit_inst<T: DisplaySink>(instr: &Instruction, out: &mut T) -> fm
panic!("impossible it operand");
};
- let inv = cond & 1 == 1;
- let condition = ConditionCode::build(*cond as u8);
+ let (inv, condition) = if *cond == 0b1111 {
+ // we've allowed *unpredictable* instruction encodings. capstone calls this condition
+ // "al" as well, so might as well follow along... and for this condition code it
+ // doesn't invert the fields either!
+ (false, ConditionCode::AL)
+ } else {
+ let inv = cond & 1 == 1;
+ (inv, ConditionCode::build(*cond as u8))
+ };
if mask & 0b0001 != 0 {
// three flags
out.write_char(if inv ^ ((mask & 0b1000) != 0) { 'e' } else { 't' })?;