diff options
| author | rva3 <rva333@protonmail.com> | 2026-02-20 03:45:01 +0200 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-02-22 03:08:10 +0000 |
| commit | fa24eedf78fb9fe2d87ac3f59763e25d3ba4462f (patch) | |
| tree | f626db67bb33d750be7304c58dca3da260257f77 /src/armv7/display.rs | |
| parent | 256c8128d82a5c5d99c1a114f3fb488b28d6b925 (diff) | |
support A1 encoding of several coprocessor instructions + SVC
initially was "implement MCR/MRC decoding", but expanded to include the
whole coprocessor space for completeness, and then SVC is right there
too.
Neon instructions in this space are still rejected, as neon support is
not really there yet.
Co-authored-by: iximeow <me@iximeow.net>
Diffstat (limited to 'src/armv7/display.rs')
| -rw-r--r-- | src/armv7/display.rs | 83 |
1 files changed, 46 insertions, 37 deletions
diff --git a/src/armv7/display.rs b/src/armv7/display.rs index f81e2cc..5ceedd6 100644 --- a/src/armv7/display.rs +++ b/src/armv7/display.rs @@ -462,18 +462,20 @@ pub(crate) fn visit_inst<T: DisplaySink>(instr: &Instruction, out: &mut T) -> fm _ => {} } } - Opcode::STCL(coproc) | - Opcode::STC(coproc) | - Opcode::STC2L(coproc) | - Opcode::STC2(coproc) | - Opcode::LDC(coproc) | - Opcode::LDCL(coproc) | - Opcode::LDC2(coproc) | - Opcode::LDC2L(coproc) => { + Opcode::STCL(coproc, _) | + Opcode::STC(coproc, _) | + Opcode::LDC(coproc, _) | + Opcode::LDCL(coproc, _) => { out.span_start_opcode(); unsafe { out.write_lt_8(instr.opcode.name())?; } + if instr.condition != ConditionCode::AL { + let name = instr.condition.name(); + // all condition codes are two characters long + out.write_char(name[0] as char)?; + out.write_char(name[1] as char)?; + } out.span_end_opcode(); out.write_fixed_size(" p")?; if coproc >= 10 { @@ -497,12 +499,18 @@ pub(crate) fn visit_inst<T: DisplaySink>(instr: &Instruction, out: &mut T) -> fm return Ok(()); } - Opcode::MRRC2(coproc, opc) | - Opcode::MCRR2(coproc, opc) => { + Opcode::MRRC(coproc, opc, _) | + Opcode::MCRR(coproc, opc, _) => { out.span_start_opcode(); unsafe { out.write_lt_8(instr.opcode.name())?; } + if instr.condition != ConditionCode::AL { + let name = instr.condition.name(); + // all condition codes are two characters long + out.write_char(name[0] as char)?; + out.write_char(name[1] as char)?; + } out.span_end_opcode(); out.write_char(' ')?; @@ -527,11 +535,17 @@ pub(crate) fn visit_inst<T: DisplaySink>(instr: &Instruction, out: &mut T) -> fm } Opcode::MRC(coproc, opc1, opc2, _) | Opcode::MCR(coproc, opc1, opc2, _) | - Opcode::CDP2(coproc, opc1, opc2) => { + Opcode::CDP(coproc, opc1, opc2, _) => { out.span_start_opcode(); unsafe { out.write_lt_8(instr.opcode.name())?; } + if instr.condition != ConditionCode::AL { + let name = instr.condition.name(); + // all condition codes are two characters long + out.write_char(name[0] as char)?; + out.write_char(name[1] as char)?; + } out.span_end_opcode(); out.write_char(' ')?; @@ -911,21 +925,15 @@ impl <T: fmt::Write, Y: YaxColors> Colorize<T, Y> for ConditionedOpcode { Opcode::HVC | Opcode::SVC | Opcode::SMC | - Opcode::LDC(_) | - Opcode::LDCL(_) | - Opcode::LDC2(_) | - Opcode::LDC2L(_) | - Opcode::STC(_) | - Opcode::STCL(_) | - Opcode::STC2(_) | - Opcode::STC2L(_) | - Opcode::MCRR2(_, _) | + Opcode::LDC(_, _) | + Opcode::LDCL(_, _) | + Opcode::STC(_, _) | + Opcode::STCL(_, _) | + Opcode::MCRR(_, _, _) | Opcode::MCR(_, _, _, _) | - Opcode::MRRC2(_, _) | + Opcode::MRRC(_, _, _) | Opcode::MRC(_, _, _, _) | - Opcode::MCRR(_, _) | - Opcode::MRRC(_, _) | - Opcode::CDP2(_, _, _) => { write!(out, "{}", colors.platform_op(self)) }, + Opcode::CDP(_, _, _, _) => { write!(out, "{}", colors.platform_op(self)) }, } } } @@ -950,23 +958,24 @@ impl Opcode { Opcode::LDRSBT => { "ldrsbt" }, Opcode::STRD => { "strd" }, Opcode::LDRD => { "ldrd" }, - Opcode::LDC(_) => { "ldc" }, - Opcode::LDCL(_) => { "ldcl" }, - Opcode::LDC2(_) => { "ldc2" }, - Opcode::LDC2L(_) => { "ldc2l" }, - Opcode::STC(_) => { "stc" }, - Opcode::STCL(_) => { "stcl" }, - Opcode::STC2(_) => { "stc2" }, - Opcode::STC2L(_) => { "stc2l" }, - Opcode::MCRR2(_, _) => { "mcrr2" }, + Opcode::LDC(_, false) => { "ldc" }, + Opcode::LDC(_, true) => { "ldc2" }, + Opcode::LDCL(_, false) => { "ldcl" }, + Opcode::LDCL(_, true) => { "ldc2l" }, + Opcode::STC(_, false) => { "stc" }, + Opcode::STC(_, true) => { "stc2" }, + Opcode::STCL(_, false) => { "stcl" }, + Opcode::STCL(_, true) => { "stc2l" }, Opcode::MCR(_, _, _, false) => { "mcr" }, Opcode::MCR(_, _, _, true) => { "mcr2" }, - Opcode::MRRC2(_, _) => { "mrrc2" }, Opcode::MRC(_, _, _, false) => { "mrc" }, Opcode::MRC(_, _, _, true) => { "mrc2" }, - Opcode::MCRR(_, _) => { "mcrr" }, - Opcode::MRRC(_, _) => { "mrrc" }, - Opcode::CDP2(_, _, _) => { "cdp2" }, + Opcode::MCRR(_, _, false) => { "mcrr" }, + Opcode::MCRR(_, _, true) => { "mcrr2" }, + Opcode::MRRC(_, _, false) => { "mrrc" }, + Opcode::MRRC(_, _, true) => { "mrrc2" }, + Opcode::CDP(_, _, _, false) => { "cdp" }, + Opcode::CDP(_, _, _, true) => { "cdp2" }, Opcode::SRS(true, true) => { "srsib" }, Opcode::SRS(false, true) => { "srsia" }, Opcode::SRS(true, false) => { "srsdb" }, |
