diff options
| author | rva3 <rva333@protonmail.com> | 2026-02-20 03:45:01 +0200 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-02-22 03:08:10 +0000 |
| commit | fa24eedf78fb9fe2d87ac3f59763e25d3ba4462f (patch) | |
| tree | f626db67bb33d750be7304c58dca3da260257f77 /src/armv7/thumb.rs | |
| parent | 256c8128d82a5c5d99c1a114f3fb488b28d6b925 (diff) | |
support A1 encoding of several coprocessor instructions + SVC
initially was "implement MCR/MRC decoding", but expanded to include the
whole coprocessor space for completeness, and then SVC is right there
too.
Neon instructions in this space are still rejected, as neon support is
not really there yet.
Co-authored-by: iximeow <me@iximeow.net>
Diffstat (limited to 'src/armv7/thumb.rs')
| -rw-r--r-- | src/armv7/thumb.rs | 40 |
1 files changed, 8 insertions, 32 deletions
diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs index e18cb38..a2809eb 100644 --- a/src/armv7/thumb.rs +++ b/src/armv7/thumb.rs @@ -4253,11 +4253,7 @@ fn decode_table_a6_30(decoder: &InstDecoder, inst: &mut Instruction, instr2: Bit let opc1 = lower2[4..8].load::<u8>(); let rt = lower2[12..16].load::<u8>(); let rt2 = instr2[0..4].load::<u8>(); - if instr2[12] { - inst.opcode = Opcode::MCRR2(coproc, opc1); - } else { - inst.opcode = Opcode::MCRR(coproc, opc1); - } + inst.opcode = Opcode::MCRR(coproc, opc1, instr2[12]); inst.operands = [ Operand::Reg(Reg::from_u8(rt)), Operand::Reg(Reg::from_u8(rt2)), @@ -4275,11 +4271,7 @@ fn decode_table_a6_30(decoder: &InstDecoder, inst: &mut Instruction, instr2: Bit // but the operand name is `opc1`! // // this is a very uninteresting typo, but fun to spot nonetheless - if instr2[12] { - inst.opcode = Opcode::MRRC2(coproc, opc1); - } else { - inst.opcode = Opcode::MRRC(coproc, opc1); - } + inst.opcode = Opcode::MRRC(coproc, opc1, instr2[12]); inst.operands = [ Operand::Reg(Reg::from_u8(rt)), Operand::Reg(Reg::from_u8(rt2)), @@ -4296,18 +4288,10 @@ fn decode_table_a6_30(decoder: &InstDecoder, inst: &mut Instruction, instr2: Bit let crd = lower2[12..16].load::<u8>(); let imm8 = lower2[0..8].load::<u16>(); - if instr2[12] { - if instr2[6] { - inst.opcode = Opcode::STC2L(coproc); - } else { - inst.opcode = Opcode::STC2(coproc); - } + if instr2[6] { + inst.opcode = Opcode::STCL(coproc, instr2[12]); } else { - if instr2[6] { - inst.opcode = Opcode::STCL(coproc); - } else { - inst.opcode = Opcode::STC(coproc); - } + inst.opcode = Opcode::STC(coproc, instr2[12]); } inst.operands = [ Operand::CReg(CReg::from_u8(crd)), @@ -4356,18 +4340,10 @@ fn decode_table_a6_30(decoder: &InstDecoder, inst: &mut Instruction, instr2: Bit // `LDC, LDC2 (immediate) on A8-393` } - if instr2[12] { - if instr2[6] { - inst.opcode = Opcode::LDC2L(coproc); - } else { - inst.opcode = Opcode::LDC2(coproc); - } + if instr2[6] { + inst.opcode = Opcode::LDCL(coproc, instr2[12]); } else { - if instr2[6] { - inst.opcode = Opcode::LDCL(coproc); - } else { - inst.opcode = Opcode::LDC(coproc); - } + inst.opcode = Opcode::LDC(coproc, instr2[12]); } inst.operands = [ Operand::CReg(CReg::from_u8(crd)), |