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| author | iximeow <me@iximeow.net> | 2026-08-02 20:28:30 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-08-02 20:28:30 +0000 |
| commit | b89b56f1e92b9559ccd11929e575db3ea2b71ced (patch) | |
| tree | 5f39d5b218a06c53d8e112ba4f045dcbd7c90d5b /src/armv7 | |
| parent | 8d4d7a3876cbca23e21c4b5c7c30abae934b6b30 (diff) | |
fix missing decode of `s` bit for wide shift/rotate ops
Diffstat (limited to 'src/armv7')
| -rw-r--r-- | src/armv7/thumb.rs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs index 45c8917..18b4526 100644 --- a/src/armv7/thumb.rs +++ b/src/armv7/thumb.rs @@ -2762,6 +2762,7 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d if !op2[3] { // `LSL`, `LSR`, `ASR`, `ROR` // v6T2 + inst.set_s(instr2[4]); let op = [ Opcode::LSL, Opcode::LSR, |