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| author | iximeow <me@iximeow.net> | 2021-10-25 00:41:03 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-10-25 00:41:07 -0700 |
| commit | ac74d253a15616dbad0256e81bf32d02b492dcc3 (patch) | |
| tree | fb771db9ddf3361717de8ad7e22adb21e6b9ffcb /src/armv8/a64.rs | |
| parent | 48542dfaeb1c48c0495d393741d20666aeb26b7e (diff) | |
shifted/extended add/sub is contingent on bit 21, not 17
the comment was even correct! but the actual check was not.
Diffstat (limited to 'src/armv8/a64.rs')
| -rw-r--r-- | src/armv8/a64.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index b6365e6..fca9e15 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -1686,7 +1686,7 @@ impl Decoder<ARMv8> for InstDecoder { let size = if sf { SizeCode::X } else { SizeCode::W }; // and operands are contingent on bit 21 - if (word & 0x20000) != 0 { + if (word & 0x20_0000) != 0 { // extended form // opt (bits 22, 23) must be 0 |