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| author | iximeow <me@iximeow.net> | 2021-12-31 02:51:52 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-12-31 02:51:52 -0800 |
| commit | ad120206e5112bcb15ab58403dd09e5baa3ea9d5 (patch) | |
| tree | afa7a95ef163cac435d9e51f0c1daff509f1420b /src/armv8/a64.rs | |
| parent | 7dd687d42293b75685fadda21ffafad1925a52de (diff) | |
sshll is weird
Diffstat (limited to 'src/armv8/a64.rs')
| -rw-r--r-- | src/armv8/a64.rs | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index f6b6f0a..2d89d3c 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -3146,6 +3146,17 @@ impl Decoder<ARMv8> for InstDecoder { (datasize, T) }; + let (datasize, T, shift) = if opcode == Opcode::SSHLL { + let new_t = match T { + SIMDSizeCode::B => SIMDSizeCode::H, + SIMDSizeCode::H => SIMDSizeCode::S, + _ /* SIMDSizeCode::S */ => SIMDSizeCode::D, + }; + (SIMDSizeCode::Q, new_t, shift) + } else { + (datasize, T, shift) + }; + if Q == 1 { if inst.opcode == Opcode::RSHRN { inst.opcode = Opcode::RSHRN2; @@ -4583,7 +4594,7 @@ impl Decoder<ARMv8> for InstDecoder { // u == 1, op == 0b00000 ]; - let (opc, (datasize_a, elemsize_a, datasize_b, elemsize_b)) = if opcode == 0b00101 && U == 1{ + let (opc, (datasize_a, elemsize_a, datasize_b, elemsize_b)) = if opcode == 0b00101 && U == 1 { let vecsize = if q == 0 { SIMDSizeCode::D } else { |