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| author | iximeow <me@iximeow.net> | 2021-10-25 19:55:07 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-10-25 19:55:07 -0700 |
| commit | b077973907857abc777383acc9638830d7745a86 (patch) | |
| tree | 0b570ec33dda4568a6165ca7e66a7294ee602fca /src/armv8/a64.rs | |
| parent | dd56b5fb73f85bcb73094097cfe35a402c1d8628 (diff) | |
madd/msub aliases
Diffstat (limited to 'src/armv8/a64.rs')
| -rw-r--r-- | src/armv8/a64.rs | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index 52c90bc..b901d21 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -804,24 +804,42 @@ impl Display for Instruction { write!(fmt, "cls")?; } Opcode::MADD => { + if let Operand::Register(_, 31) = self.operands[3] { + return write!(fmt, "mul {}, {}, {}", self.operands[0], self.operands[1], self.operands[2]) + } write!(fmt, "madd")?; } Opcode::MSUB => { + if let Operand::Register(_, 31) = self.operands[3] { + return write!(fmt, "mneg {}, {}, {}", self.operands[0], self.operands[1], self.operands[2]) + } write!(fmt, "msub")?; } Opcode::SMADDL => { + if let Operand::Register(_, 31) = self.operands[3] { + return write!(fmt, "smull {}, {}, {}", self.operands[0], self.operands[1], self.operands[2]) + } write!(fmt, "smaddl")?; } Opcode::SMSUBL => { + if let Operand::Register(_, 31) = self.operands[3] { + return write!(fmt, "smnegl {}, {}, {}", self.operands[0], self.operands[1], self.operands[2]) + } write!(fmt, "smsubl")?; } Opcode::SMULH => { write!(fmt, "smulh")?; } Opcode::UMADDL => { + if let Operand::Register(_, 31) = self.operands[3] { + return write!(fmt, "umull {}, {}, {}", self.operands[0], self.operands[1], self.operands[2]) + } write!(fmt, "umaddl")?; } Opcode::UMSUBL => { + if let Operand::Register(_, 31) = self.operands[3] { + return write!(fmt, "umnegl {}, {}, {}", self.operands[0], self.operands[1], self.operands[2]) + } write!(fmt, "umsubl")?; } Opcode::UMULH => { |