diff options
| author | iximeow <me@iximeow.net> | 2021-12-27 19:01:58 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-12-27 19:01:58 -0800 |
| commit | 4e28a1078e93c15bc8b9076504f2eba4656ccf76 (patch) | |
| tree | 5aae344aedc673cbc28d0e39714daebc3710be4a /src/armv8/a64.rs | |
| parent | 03b3b1b917cb138e1ef05b302a41e198d933323f (diff) | |
fcmp/fcmpe fixes
Diffstat (limited to 'src/armv8/a64.rs')
| -rw-r--r-- | src/armv8/a64.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index 37cec04..408bc13 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -4804,14 +4804,14 @@ impl Decoder<ARMv8> for InstDecoder { return Err(DecodeError::InvalidOperand); }; - inst.opcode = if opcode & 0b1_0000 != 0 { + inst.opcode = if opcode2 & 0b1_0000 != 0 { Opcode::FCMPE } else { Opcode::FCMP }; inst.operands = [ Operand::SIMDRegister(precision, Rn as u16), - if Rm == 0 { + if opcode2 & 0b01000 != 0 { // and, sugguested, Rm == 0 Operand::Immediate(0) } else { Operand::SIMDRegister(precision, Rm as u16) |