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author | iximeow <me@iximeow.net> | 2024-03-16 11:50:08 -0700 |
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committer | iximeow <me@iximeow.net> | 2024-03-16 11:50:08 -0700 |
commit | 97c724d483c309b95cba75dae3445b069e8b7915 (patch) | |
tree | 419fa6126ce155d44328ad7e4109dd1021a57366 /src/armv8/a64.rs | |
parent | 17f9330abed70364edc404f95471298e2b9bd29a (diff) |
fix ldrsw register size
also unignore tests that would have caught this
fix test expectation that predated using pc-relative syntax
and fix a test that expected an instruction to be disassembled as "invalid" successfully, rather than returning an error
Diffstat (limited to 'src/armv8/a64.rs')
-rw-r--r-- | src/armv8/a64.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index a1fc8bf..55fbbed 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -8433,7 +8433,7 @@ impl Decoder<ARMv8> for InstDecoder { } 0b10 => { inst.opcode = Opcode::LDRSW; - SizeCode::W + SizeCode::X } 0b11 => { inst.opcode = Opcode::PRFM; |