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authoriximeow <me@iximeow.net>2021-12-29 01:58:27 -0800
committeriximeow <me@iximeow.net>2021-12-29 01:58:27 -0800
commit611a375a524fcdee098ae7fae00c5498ff0d1465 (patch)
treeb4e71d2d267797a946382151b6de4a79b47a61c9 /src/armv8
parent9967fba9f8f8449626692e336ff4d44823f036fc (diff)
stxrb memory operand error
Diffstat (limited to 'src/armv8')
-rw-r--r--src/armv8/a64.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index 9d94c1a..8b96f60 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -6844,14 +6844,14 @@ impl Decoder<ARMv8> for InstDecoder {
inst.operands = [
Operand::Register(SizeCode::W, Rs),
Operand::Register(SizeCode::W, Rt),
- Operand::RegisterOrSP(SizeCode::X, Rn),
+ Operand::RegOffset(Rn, 0),
Operand::Nothing,
];
} else if Lo1 == 0b10 {
// load ops
inst.operands = [
Operand::Register(SizeCode::W, Rt),
- Operand::RegisterOrSP(SizeCode::X, Rn),
+ Operand::RegOffset(Rn, 0),
Operand::Nothing,
Operand::Nothing,
];