aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authoriximeow <me@iximeow.net>2019-08-04 19:12:25 -0700
committeriximeow <me@iximeow.net>2020-01-12 17:28:07 -0800
commited2a36de61a295f7c17378598f5a60e7de9d8b8a (patch)
tree3771e08452b69dca8325d27561a687cfe4096ae8 /src
parent964ca6566c61b0c7cd48d8801c74d1b4dfe0b7a2 (diff)
fix issue with incorrectly decoding register shifts
Diffstat (limited to 'src')
-rw-r--r--src/armv7.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/armv7.rs b/src/armv7.rs
index 52061c7..a5467e5 100644
--- a/src/armv7.rs
+++ b/src/armv7.rs
@@ -487,7 +487,7 @@ fn format_shift<T: std::fmt::Write>(f: &mut T, Rm: u8, shift: ShiftSpec, colors:
},
ShiftSpec::Register(v) => {
let tpe = v & 0x3;
- let Rs = v >> 2;
+ let Rs = v >> 3;
write!(f, "{}, {} {}", reg_name_colorize(Rm, colors), shift_tpe_to_str(tpe), reg_name_colorize(Rs, colors))
},
}