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authoriximeow <me@iximeow.net>2024-03-16 23:35:23 +0000
committeriximeow <me@iximeow.net>2024-03-16 23:35:23 +0000
commit2b0930355d87d7f195a7ff05d18b09b61a5ea490 (patch)
tree3498b64fd78a218378ee9266251be10c3920f9ce /src
parentedfbf64598793284ddc3554dd2b264c1491d9a2f (diff)
ldrab and ldraa tests, fix immediate decoding
Diffstat (limited to 'src')
-rw-r--r--src/armv8/a64.rs10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index cdee6d5..de7a743 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -9105,8 +9105,10 @@ impl Decoder<ARMv8> for InstDecoder {
// V==0
let w = (word >> 11) & 1;
let imm9 = ((word >> 12) & 0b1_1111_1111) as i16;
- let imm9 = ((imm9 << 7) >> 7) as i32;
- let imm9 = imm9 << 3; // `simm` is stored as a multiple of 8
+ let S = ((word >> 22) & 1) as i16;
+ let imm10 = imm9 | (S << 9);
+ let imm10 = imm10 << 3; // `simm` is stored as a multiple of 8
+ let imm10 = ((imm10 << 3) >> 3) as i32;
let m = (word >> 23) & 1;
let size = (word >> 30) & 0b11;
if size != 0b11 {
@@ -9122,9 +9124,9 @@ impl Decoder<ARMv8> for InstDecoder {
inst.operands = [
Operand::Register(SizeCode::X, Rt),
if w == 0 {
- Operand::RegPreIndex(Rn, imm9, false)
+ Operand::RegPreIndex(Rn, imm10, false)
} else {
- Operand::RegPreIndex(Rn, imm9, true)
+ Operand::RegPreIndex(Rn, imm10, true)
},
Operand::Nothing,
Operand::Nothing,