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authoriximeow <me@iximeow.net>2022-01-01 01:13:12 -0800
committeriximeow <me@iximeow.net>2022-01-01 01:13:12 -0800
commiteb867d51ed8ad3b45d710f4ae3eb2fbb52605cb6 (patch)
tree8bed203f88eaba3110e32f198e7eae13042cd5ee /src
parentc6042657deccd52aee3376c4bb618fe97b39e5ca (diff)
test expectation cleanup
Diffstat (limited to 'src')
-rw-r--r--src/armv8/a64.rs12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index a1f977f..eb709d0 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -297,9 +297,9 @@ impl Display for Instruction {
};
let imm = if let Operand::Register(size, _) = self.operands[0] {
if size == SizeCode::W {
- (imm as u32) as i32 as i64
+ imm as u32 as u64
} else {
- imm as i64
+ imm
}
} else {
unreachable!("movn operand 0 is always Register");
@@ -314,9 +314,9 @@ impl Display for Instruction {
};
let imm = if let Operand::Register(size, _) = self.operands[0] {
if size == SizeCode::W {
- (imm as u32) as i32 as i64
+ imm as u32 as u64
} else {
- imm as i64
+ imm
}
} else {
unreachable!("movn operand 0 is always Register");
@@ -2862,7 +2862,7 @@ impl Display for Operand {
}
}
Operand::Immediate(i) => {
- write!(fmt, "#{:x}", *i)
+ write!(fmt, "#{:#x}", *i)
},
Operand::ImmediateDouble(d) => {
write!(fmt, "#{:0.1}", d)
@@ -2932,7 +2932,7 @@ impl Display for Operand {
*amount == 0 {
write!(fmt, "[{}, {}, {}]", Operand::RegisterOrSP(SizeCode::X, *reg), Operand::Register(*index_size, *index_reg), extend)
} else {
- write!(fmt, "[{}, {}, {} #{:#x}]", Operand::RegisterOrSP(SizeCode::X, *reg), Operand::Register(*index_size, *index_reg), extend, amount)
+ write!(fmt, "[{}, {}, {} #{}]", Operand::RegisterOrSP(SizeCode::X, *reg), Operand::Register(*index_size, *index_reg), extend, amount)
}
}
Operand::RegPreIndex(reg, offset, wback_bit) => {