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authoriximeow <me@iximeow.net>2021-10-25 00:52:58 -0700
committeriximeow <me@iximeow.net>2021-10-25 00:52:58 -0700
commitdd56b5fb73f85bcb73094097cfe35a402c1d8628 (patch)
tree6fccb24161155921c5d3c8f579732ad26bf86b46 /src
parentc74982cfcc02e00ca3776412417bba07d3182bbf (diff)
csneg/csinv aliases
Diffstat (limited to 'src')
-rw-r--r--src/armv8/a64.rs9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index 9e2afcc..52c90bc 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -736,6 +736,13 @@ impl Display for Instruction {
write!(fmt, "csel")?;
}
Opcode::CSNEG => {
+ if let (Operand::Register(size, rn), Operand::Register(_size, rm), Operand::ConditionCode(cond)) = (self.operands[1], self.operands[2], self.operands[3]) {
+ if rn == rm {
+ return write!(fmt, "cneg {}, {}, {}", self.operands[0], self.operands[2], Operand::ConditionCode(cond ^ 0x01));
+ }
+ } else {
+ unreachable!("operands 2 and 3 are always registers");
+ }
write!(fmt, "csneg")?;
}
Opcode::CSINC => {
@@ -758,6 +765,8 @@ impl Display for Instruction {
(Operand::Register(_, n), Operand::Register(_, m), Operand::ConditionCode(cond)) => {
if n == m && n != 31 && cond < 0b1110 {
return write!(fmt, "cinv {}, {}, {}", self.operands[0], self.operands[1], Operand::ConditionCode(cond ^ 0x01))
+ } else if n == m && n == 31 {
+ return write!(fmt, "csetm {}, {}", self.operands[0], Operand::ConditionCode(cond ^ 0x01));
}
}
_ => {}