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authorGrond <grond@grondhaus.net>2026-06-22 13:03:32 -0700
committeriximeow <me@iximeow.net>2026-07-28 02:53:24 +0000
commit03b7860359a9bdff793419367563974db335e45e (patch)
treee93fb929d8adec23a70d3548e9a1bfcd82269659 /src
parent44f91bf710081d98b465252487a6b168b2f2597e (diff)
Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2
Diffstat (limited to 'src')
-rw-r--r--src/armv7.rs11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/armv7.rs b/src/armv7.rs
index ada486a..2901508 100644
--- a/src/armv7.rs
+++ b/src/armv7.rs
@@ -1492,6 +1492,17 @@ impl Decoder<ARMv7> for InstDecoder {
}
}
0b11 => {
+ // We know the instruction looks like this...
+ // |1 1 1 1|1 1 1|x x x x|x|x x x x|x x x x|x x x x x|x x|x|x x x x|
+ // ^ We need to check that this bit is zero, if any of the
+ // instructions decoded in this block are to match
+ // correctly.
+ // See A5-214 for the table that shows the required forms for these
+ // instructions.
+ if (op1 >> 4) & 1 != 0 {
+ return Err(DecodeError::InvalidOpcode);
+ }
+
// operands are shared between cdp2 and mcr2/mrc2, but Rt is repurposed as
// CRd
let CRm = word as u8 & 0b1111;