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| author | iximeow <me@iximeow.net> | 2019-08-04 19:12:25 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2020-01-12 17:28:07 -0800 |
| commit | 8b9d5f9c6003864870dccfe2c0f71729d4b99564 (patch) | |
| tree | f1f12477081ec1da085ca0a931f7e4422e22f542 /test/armv7.rs | |
| parent | dc9366f430874c25e4e44e2a365efea5fcc43382 (diff) | |
fix issue with incorrectly decoding register shifts
Diffstat (limited to 'test/armv7.rs')
| -rw-r--r-- | test/armv7.rs | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/test/armv7.rs b/test/armv7.rs index c76cb4a..af5336c 100644 --- a/test/armv7.rs +++ b/test/armv7.rs @@ -163,6 +163,21 @@ fn test_decode_mov() { #[test] fn test_decode_arithmetic() { test_decode( + [0x18, 0x1d, 0x00, 0x00], + Instruction { + condition: ConditionCode::EQ, + opcode: Opcode::AND, + operands: Operands::ThreeOperandWithShift( + 1, 0, 8, ShiftSpec::Register(104) + ), + s: false + } + ); + test_display( + [0x18, 0x1d, 0x00, 0x00], + "andeq r1, r0, r8, lsl sp", + ); + test_decode( [0x03, 0x30, 0x8f, 0xe0], Instruction { condition: ConditionCode::AL, |