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authoriximeow <me@iximeow.net>2019-08-04 19:12:25 -0700
committeriximeow <me@iximeow.net>2020-01-12 17:28:07 -0800
commited2a36de61a295f7c17378598f5a60e7de9d8b8a (patch)
tree3771e08452b69dca8325d27561a687cfe4096ae8 /test
parent964ca6566c61b0c7cd48d8801c74d1b4dfe0b7a2 (diff)
fix issue with incorrectly decoding register shifts
Diffstat (limited to 'test')
-rw-r--r--test/armv7.rs19
-rw-r--r--test/test.rs2
2 files changed, 18 insertions, 3 deletions
diff --git a/test/armv7.rs b/test/armv7.rs
index 6fd46c3..7715585 100644
--- a/test/armv7.rs
+++ b/test/armv7.rs
@@ -166,12 +166,27 @@ fn test_decode_arithmetic() {
[0x58, 0x37, 0x01, 0x40],
Instruction {
condition: ConditionCode::MI,
- opcode: AND,
- operands: Operands::ThreeOperands(3, 1, 8),
+ opcode: Opcode::AND,
+ operands: Operands::ThreeOperand(3, 1, 8),
s: false
}
);
test_decode(
+ [0x18, 0x1d, 0x00, 0x00],
+ Instruction {
+ condition: ConditionCode::EQ,
+ opcode: Opcode::AND,
+ operands: Operands::ThreeOperandWithShift(
+ 1, 0, 8, ShiftSpec::Register(104)
+ ),
+ s: false
+ }
+ );
+ test_display(
+ [0x18, 0x1d, 0x00, 0x00],
+ "andeq r1, r0, r8, lsl sp",
+ );
+ test_decode(
[0x03, 0x30, 0x8f, 0xe0],
Instruction {
condition: ConditionCode::AL,
diff --git a/test/test.rs b/test/test.rs
index 7dd54ea..72b7e50 100644
--- a/test/test.rs
+++ b/test/test.rs
@@ -5,5 +5,5 @@ extern crate test;
extern crate yaxpeax_arch;
extern crate yaxpeax_arm;
-// mod armv7;
+mod armv7;
mod armv8;