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| author | Grond <grond@grondhaus.net> | 2026-06-23 14:02:51 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-07-28 02:53:24 +0000 |
| commit | 40743d84ffc8bbe0a4e24b9af4d65d58a1367b23 (patch) | |
| tree | 3e6f4a789bda85fc5334ea682c5c2686494fab80 /tests/armv7/mod.rs | |
| parent | 1bff2519a50ac4e3ca98b4d874f70c02628c3f4a (diff) | |
Fix the handling of arithmetic register shifts with zero immediates
Diffstat (limited to 'tests/armv7/mod.rs')
| -rw-r--r-- | tests/armv7/mod.rs | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/armv7/mod.rs b/tests/armv7/mod.rs index 8f413ca..9a9e718 100644 --- a/tests/armv7/mod.rs +++ b/tests/armv7/mod.rs @@ -696,6 +696,19 @@ fn test_decode_mul() { ); } +#[test] +fn test_register_shift_rotate() { + test_armv6([0xec, 0x02, 0x00, 0x00], "andeq r0, r0, ip, ror 5"); + test_armv6([0xa0, 0x33, 0x0b, 0x00], "andeq r3, fp, r0, lsr 7"); + test_armv6([0xa4, 0x33, 0x0b, 0x00], "andeq r3, fp, r4, lsr 7"); + test_armv6([0xa0, 0x7d, 0x0b, 0x00], "andeq r7, fp, r0, lsr 27"); + + // When an LSR or ASR shift has an encoded immediate of zero, it actually means that the + // applied shift is 32. + test_armv6([0x21, 0x00, 0x20, 0x00], "eoreq r0, r0, r1, lsr 32"); + test_armv6([0x41, 0x00, 0x20, 0x00], "eoreq r0, r0, r1, asr 32"); +} + static INSTRUCTION_BYTES: [u8; 4 * 60] = [ 0x24, 0xc0, 0x9f, 0xe5, 0x00, 0xb0, 0xa0, 0xe3, |